IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 237

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 2: Arithmetic Library
Pipelined Adder
Table 2–43. Parallel Adder Subtractor Block I/O Formats (Part 2 of 2)
Figure 2–17. Parallel Adder Subtractor Block Example
Pipelined Adder
© June 2010 Altera Corporation
I/O
O
Notes to
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit.
(2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned
(3) I1
(4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath
integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit.
bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
O1
ceil(log2(n))].[max(Ri)]
[L].[R]
[max(Li) +
Table
Simulink (2),
is an input port. O1
2–43:
(3)
Figure 2–17
The Pipelined Adder block is a pipelined adder and subtractor that performs the
following calculation:
Use the optional ovl port an overflow with signed arithmetic or as a carry out with
unsigned arithmetic. For unsigned subtraction, the output is 1 when no overflow
occurs.
Table 2–44
Table 2–44. Pipelined Adder Block Inputs and Outputs
a
b
cin
addsub
ena
aclr
r
ovl
[L].[R]
r = a + b + cin (when addsub = 1)
r = a - b + cin -1 (when addsub = 0)
Signal
O1: out STD_LOGIC_VECTOR({max(Li) + ceil(log2(n)) + max(Ri) - 1} DOWNTO 0) Implicit
is an output port.
shows the Pipelined Adder block inputs and outputs.
shows an example with the Parallel Adder Subtractor block.
Input
Input
Input
Input
Input
Input
Output
Output
Direction
Preliminary
Operand a.
Operand b.
Optional carry in.
Optional control (1= add, 0 = subtract).
Optional clock enable.
Optional asynchronous clear.
Result r.
Optional overflow (signed) or carry out (unsigned).
VHDL
(Note 1)
Description
DSP Builder Standard Blockset Libraries
Type
2–29
(4)