IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 61

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 3: Design Rules and Procedures
Timing Semantics Between Simulink and HDL Simulation
Startup & Initial Conditions
DSP Builder Global Reset Circuitry
© June 2010 Altera Corporation
1
The testbench includes a global reset for each clock domain. All blocks (except the
HDL Import and MegaCore function blocks) automatically connect any reset on the
hardware to the global asynchronous reset for the clock domain.
When a block explicitly declares an asynchronous reset, this reset is ORed with the
global reset.
A Global Reset block (SCLR), which corresponds to this hardware signal is in the
Altera DSP Builder Blockset IO & Bus library.
The global reset signal is reset before meaningful simulation. When converting from
the Simulink domain to the hardware domain, the reset period is before the Simulink
simulation begins. Therefore, in Simulink simulation, the Global Reset block
outputs only a constant zero and has no simulation behavior. Connect the hardware to
reset, and thus reset at the start of a ModelSim testbench simulation.
DSP blocks or MegaCore functions may have additional initial conditions or startup
states that are not automatically reset by the global reset signal.
By default, Simulink does not graphically display the clock enable and reset input
pins on DSP Builder registered blocks. When DSP Builder converts a design to HDL, it
automatically connects the implied clock enable and reset pins.
If you turn on the optional ports in the Block Parameters dialog box for each of the
DSP Builder registered blocks, you can access and drive the clock enable and reset
input pins graphically in the Simulink software.
In the HDL domain, the registered DSP Builder blocks uses an asynchronous reset, as
this behavioral VHDL code example shows:
In addition, when targeting a development board, the Block Parameters dialog box
for the DSP Board configuration block typically includes a Global Reset Pin selection
box where you can choose from a list of pins that correspond to the DIP and
push-button switches.
The reset logic polarity can be either active-high or active-low. When you select
active-low, the value of the reset signal in Simulink simulation is still 0 for inactive
and 1 for active. However, DSP Builder inserts a NOT gate on the input pin in the
generated hardware. The value of the reset signal in simulation is therefore the value
as it exists across the internal design, rather then the value at the input pin.
Quartus
of the logic element look-up table to instantiate the function. The HDL simulates
correctly in this case because the testbench produces the reset input as required.
process(CLOCK, RESET)
begin
end
if RESET = '1' then
else if CLOCK'event and CLOCK = '1' then
end if;
®
II synthesis interprets this reset as an asynchronous reset, and uses an input
dout <= (others => '0');
dout <= din;
Preliminary
DSP Builder Standard Blockset User Guide
3–17