IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 292

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

5–6
Avalon-MM Slave
Table 5–3. Signals Supported by the Avalon-MM Slave Block
DSP Builder Standard Blockset Libraries
address
read
readdata
write
writedata
byteenable
readyfordata
dataavailable
endofpacket
readdatavalid
waitrequest
beginbursttransfer Output
burstcount
irq
begintransfer
chipselect
Signal
1
The Avalon-MM Slave block defines a collection of ports for connection to an SOPC
Builder system when your design functions as an Avalon-MM slave interface.
Table 5–3
The direction in
interface.
Table 5–4
Output
Output
Input
Output
Output
Output
Input
Input
Input
Input
Input
Output
Input
Output
Output
Direction
lists the signals supported by the Avalon-MM Slave block.
shows the Avalon-MM Slave block parameters.
Address lines to the slave port. Specifies a word offset into the slave address
space.
Available when Read or Read/Write address type is chosen. Read-request
signal. Not required if there are no read transfers. If used, also use readdata.
Available when Read or Read/Write address type is chosen. Data lines for read
transfers. Not required if there are no read transfers. If used, also use read.
Available when Write or Read/Write address type is chosen. Write-request
signal. Not required if there are no write transfers. If used, also use
writedata.
Available when Write or Read/Write address type is chosen. Data lines for write
transfers. Not required if there are no write transfers. If used, also use write.
Available when Allow Byte Enable is on and the bit width is greater than 8.
Byte-enable signals to enable specific byte lane(s) during write transfers to
memories of width greater than 8 bits. If used, also use writedata.
Available when Write or Read/Write access is chosen and Allow Flow Control is
on. Indicates that the peripheral is ready for a write transfer.
Available when Read or Read/Write access is chosen and Allow Flow Control is
on. Indicates that the peripheral is ready for a read transfer.
Available when Allow Flow Control is on. Indicates an end-of-packet condition.
Available when Allow Pipeline Transfers is on and variable read latency is
chosen. Marks the rising clock edge when readdata asserts.
Available when variable wait-state format is chosen. Use to stall the interface
when the slave port cannot respond immediately.
Available when Allow Burst Transfers is on. Asserted for the first cycle of a burst
to indicate when a burst transfer is starting.
Available when Allow Burst Transfers is on. Indicates the number of transfers in
a burst. If used, also use waitrequest.
Available when Output IRQ is on. Interrupt request. Asserted when a port needs
to be serviced.
Available when Receive Begin Transfer is on. Asserted during the first cycle of
every transfer.
Available when Use Chip Select is on. The slave port ignores all other
Avalon-MM signal inputs unless chipselect is asserted.
Table 5–3
refers to the direction in respect of the DSP Builder block
Preliminary
Description
© June 2010 Altera Corporation
Chapter 5: Interfaces Library
Avalon-MM Slave