IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 250

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

3–4
Complex AddSub
Table 3–5. Complex AddSub Block Parameters
DSP Builder Standard Blockset Libraries
Number of Inputs
Add (+) Sub (–)
Enable Pipeline
Clock Phase Selection
Use Enable Port
Use Asynchronous Clear Port
Name
The Complex AddSub block performs addition or subtraction on a specified number
of scalar complex inputs.
Table 3–4
Table 3–4. Complex AddSub Block Inputs and Outputs
Table 3–5
+ or –
ena
aclr
R
Signal
>= 2
User defined Specify addition or subtraction operation for each port with the characters +
On or Off
User Defined When you enable pipeline, you can specify the phase selection as a binary
On or Off
On or Off
shows the Complex AddSub block inputs and outputs.
shows the Complex AddSub block parameters.
Value
Input
Input
Input
Output
Direction
Specifies the number of input wires to combine.
and –. For example + – + implements +a – b + c for three ports.
DSP Builder implements the block as a tree of 2-input adders. Each
consecutive pair of inputs are + +, + – or – +. However, none of the input
adders can have two consecutive subtractions. Thus, + – – + is valid (as the
two input adders are parameterized + – and – +), + – – + + is also valid but
+ + – – + is not valid.
Missing operators are assumed to be +.
When this option is on, DSP Builder registers the output from each stage in
the adder tree, resulting in a pipeline length that is equal to
ceil(log2(number of inputs)).
string, where a 1 indicates the phase in which the block is enabled. For
example:
Turn on to use the clock enable input (ena).
Turn on to use the asynchronous clear input (aclr).
1—The block is always enabled and captures all data passing through
the block (sampled at the rate 1).
10—The block is enabled every other phase and every other data
(sampled at the rate 1) passes through.
0100—The block is enabled on the second phase of and only the
second data of (sampled at the rate 1) passes through. That is, the data
on phases 1, 3, and 4 do not pass through the block.
Preliminary
Complex inputs.
Optional clock enable.
Optional asynchronous clear.
Result.
Description
Description
Chapter 3: Complex Type Library
© June 2010 Altera Corporation
Complex AddSub