IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 304

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

5–18
Error Handling
Avalon-ST Sink
DSP Builder Standard Blockset Libraries
1
The ratio of input fields to output fields must be constant.
For example, Red,Red,Green,Blue does not map to (Red,Green,Blue)2
because each output packet requires one input packet for Red, but two input packets
for Green and Blue.
DSP Builder supports multiple interfaces but the packet ratio must be constant across
all {input interface, output interface} pairs.
For example, two input interfaces with the formats (Red,Green)2 and Blue map to
output interface (Red)6,Blue(3),Green(6) because three input packets are
required for two output packets for all input and output pairs. The same inputs do not
map to (Red)3,Blue(3),Green(3), because to make two output packets, three of
the first input's packets and six of the second input's packets are required.
DSP Builder does not support packets of unknown length.
The PFC contains internal counters that keep track of the current position in the
packet for each input and uses these counters to detect frame delineation errors. Every
time a startofpacket or endofpacket signal asserts on an input interface, the
PFC uses its knowledge of the frame structure to ensure that the assertion is on a valid
cycle. For PFC variants where the packet size is known, the PFC also checks that the
startofpacket and endofpacket signals assert when they should do, and are not
missed.
The PFC only has a single output error bit to report frame delineation errors. The
output error bit asserts on all outputs as soon as DSP Builder detects an error, and it
asserts for each output interface independently until an endofpacket asserts for that
output interface.
After the endofpacket asserts, the PFC presents no more data to that output
interface. When all output interfaces stop, the PFC resets and resumes normal
operation. The PFC stops independently on the endofpacket signal for each output,
and components downstream of the PFC should never see partial frames.
While errors assert to the output interfaces and the core is reset, the input interfaces
are not back pressured. This action prevents loss of any synchronization between
input interfaces by uneven back pressuring during error conditions.
When the PFC starts again, it waits until it sees a startofpacket signal for each
input interface before accepting data for that interface. It is not possible to guarantee
synchronization of output interfaces when frame delineation errors are present.
The PFC does not support relaying errors from an upstream component to a
downstream component.
When simulating the PFC block, connect the reset port to a pulse generator (such as
the Single Pulse block in the DSP Builder Gate & Control library) that is
configured to output an initial 0, then a 1 for the remainder of the simulation.
The Avalon-ST Sink block defines a collection of ports for connection to an SOPC
Builder system when your design functions as an Avalon-ST sink.
Preliminary
© June 2010 Altera Corporation
Chapter 5: Interfaces Library
Avalon-ST Sink