IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 228

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

2–20
Table 2–29. Integrator Block Parameters
Table 2–30. Integrator Block I/O Formats
Figure 2–12. Integrator Block Design Example
Magnitude
Table 2–31. Magnitude Block I/O Formats (Part 1 of 2)
DSP Builder Standard Blockset Libraries
Use Enable Port
Use Synchronous Clear Port On or Off
I
O
Notes to
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit.
(2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned
(3) I1
(4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath
I
I/O
I/O
integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit.
bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
I1
I2
I3
O1
I1
[L].[R]
[L1].[0]
[1]
[1]
[L1].[R1]
[L1].[0]
Table
Simulink (2),
Simulink (2),
is an input port. O1
Name
2–30:
(3)
(3)
Table 2–30
Figure 2–12
The scalar Magnitude block returns the absolute value of the incoming signed binary
fractional bus.
The Magnitude block has no parameters.
Table 2–31
[L].[R]
I1: in STD_LOGIC_VECTOR({L1 - 1} DOWNTO 0)
I2: STD_LOGIC
I3: STD_LOGIC
O1: out STD_LOGIC_VECTOR({L1 - 1} DOWNTO 0)
I1: in STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0)
On or Off
is an output port.
shows the Integrator block I/O formats.
shows the Magnitude block I/O formats.
Value
shows an example of the Integrator Block.
(Note 1)
Turn on to use the clock enable input (ena).
Turn on to use the synchronous clear input (sclr).
Preliminary
(Note 1)
VHDL
VHDL
Description
© June 2010 Altera Corporation
Chapter 2: Arithmetic Library
Explicit
Explicit
Implicit
Type
Type
(4)
(4)
Magnitude