IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 359

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 9: Storage Library
Serial To Parallel
Table 9–28. Serial To Parallel Block Parameters
Table 9–29. Serial To Parallel Block I/O Formats
Figure 9–10. Serial To Parallel Block Example
© June 2010 Altera Corporation
Data Bus Type
[number of bits].[] >= 0
[].[number of bits] >= 0
Serial Bit Order
Use Enable Port
Use Synchronous
Clear Port
I
O
Notes to
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit.
(2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned
(3) I1
(4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath
I/O
integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit.
bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
I1
I2
I3
O1
[L].[R]
Name
[1]
[1]
[1]
[L1].[R1]
Table
Simulink (2),
is an input port. O1
9–29:
Signed Integer,
Signed Fractional,
Unsigned Integer
(Parameterizable)
(Parameterizable)
MSB First, LSB First Transmit the MSB or LSB first.
On or Off
On or Off
Table 9–28
Table 9–29
Figure 9–10
(3)
[L].[R]
Value
is an output port.
I1: in STD_LOGIC
I2: in STD_LOGIC
I3: in STD_LOGIC
O1: in STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0)
shows the Serial To Parallel block parameters.
shows the Serial To Parallel block I/O formats.
shows an example with the Serial To Parallel block.
The bus type format.
Specify the number of bits stored on the left side of the binary point including
the sign bit.
Specify the number of bits stored on the right side of the binary point. This
option applies only to signed fractional formats.
Turn on to use the clock enable input.
Turn on to use the synchronous clear port (sclr).
(Note 1)
Preliminary
VHDL
Description
DSP Builder Standard Blockset Libraries
Type
Explicit
Explicit
9–19
(4)