IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 332

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

7–2
Table 7–2. Multi-Rate DFF Block Parameters
Table 7–3. Multi-Rate DFF Block I/O Formats
Figure 7–1. Multirate DFF Block Example
DSP Builder Standard Blockset Libraries
Number of Pipeline
Stages
Use Base Clock
Clock Name
Use Enable Port
Use Synchronous
Clear Port
I
O
Notes to
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit.
(2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned
(3) I1
(4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath
I/O
integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit.
bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
I1
I2
I3
O1
[L].[R]
Name
[L].[R]
[1]
[1]
[L].[R]
Table
Simulink (2),
is an input port. O1
7–3:
>= 1
(Parameterizable)
On or Off
User specified
On or Off
On or Off
Table 7–2
Table 7–3
Figure 7–1
(3)
[L].[R]
Value
is an output port.
I1: in STD_LOGIC_VECTOR({L + R - 1} DOWNTO 0)
I2: in STD_LOGIC
I3: in STD_LOGIC
O1: out STD_LOGIC_VECTOR({L + R - 1} DOWNTO 0)
shows the Multi-Rate DFF block parameters.
shows the Multi-Rate DFF block I/O formats.
shows an design example with the Multi-Rate DFF block.
Turn on to use the base clock.
Adds more pipeline stages to the block. Increased delay reduces the likelihood of
metastability.
Specify the name of the clock signal.
Turn on to use the clock enable input (ena).
Turn on to use the synchronous clear input (sclr).
(Note 1)
Preliminary
VHDL
Description
© June 2010 Altera Corporation
Chapter 7: Rate Change Library
Multi-Rate DFF
Type
Implicit
Implicit
(4)