IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 90

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

5–2
Figure 5–1. System-Level Design Flow
HIL Requirements
DSP Builder Standard Blockset User Guide
5. Scan for JTAG cables and hardware devices connected to the local host or any
6. Program the board that contains your target FPGA.
7. Simulate the combined software and hardware system in Simulink.
Figure 5–1
The HIL block has the following requirements:
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remotely enabled hosts.
1
An FPGA board with a JTAG interface (Stratix, Stratix II, Stratix III, Cyclone,
Cyclone II, or Cyclone III device).
A valid Quartus II project that contains a single clock domain from Simulink. DSP
Builder creates an internal Quartus II project when you run Signal Compiler.
A JTAG download cable (for example, a ByteBlasterMV™, ByteBlaster™ II,
ByteBlaster, MasterBlaster™, or USB-Blaster™ cable).
A maximum of one HIL block for each JTAG download cable.
When using a HIL block in a Simulink model, set a fixed-step, single
tasking solver.
shows this system-level design flow using DSP Builder.
Preliminary
© June 2010 Altera Corporation
Chapter 5: Using HIL
HIL Requirements