IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 21

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 1: About DSP Builder
General Description
General Description
High-Speed DSP with Programmable Logic
Interoperability with the Advanced Blockset
© June 2010 Altera Corporation
f
f
Digital signal processing (DSP) system design in Altera programmable logic devices
(PLDs) requires both high-level algorithm and hardware description language (HDL)
development tools.
The Altera DSP Builder integrates these tools by combining the algorithm
development, simulation, and verification capabilities of The MathWorks MATLAB
and Simulink system-level design tools with VHDL and Verilog HDL design flows,
including the Altera Quartus II software.
DSP Builder shortens DSP design cycles by helping you create the hardware
representation of a DSP design in an algorithm-friendly development environment.
You can combine existing MATLAB functions and Simulink blocks with Altera
DSP Builder blocks and Altera intellectual property (IP) MegaCore functions to link
system-level design and implementation with DSP algorithm development. In this
way, DSP Builder allows system, algorithm, and hardware designers to share a
common development platform.
The DSP Builder Signal Compiler block reads Simulink Model Files (.mdl) that
contain other DSP Builder blocks and MegaCore functions. Signal Compiler then
generates the VHDL files and Tcl scripts for synthesis, hardware implementation, and
simulation.
Programmable logic offers compelling performance advantages over dedicated DSP
processors. Think of programmable logic as an array of elements, each of which you
can configure as a complex processor routine.
You can link these routines together in serial (the same way that a DSP processor
executes them), or connect them in parallel. When connected in parallel, they give
many times better performance than standard DSP processors by executing hundreds
of instructions at the same time.
Algorithms that benefit from this improved performance include forward-error
correction (FEC), modulation and demodulation, and encryption.
DSP Builder includes an optional advanced blockset.
For more information about the advanced blockset, refer to
Advanced Blockset
For more information about the differences between the standard and advanced
blocksets and about design flows that combine both blocksets, refer to
Introduction to DSP Builder
in the DSP Builder Handbook.
in the DSP Builder Handbook.
Preliminary
DSP Builder Standard Blockset User Guide
Volume 3: DSP Builder
Volume 1:
1–3