IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 295

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 5: Interfaces Library
Avalon-MM Read FIFO
Avalon-MM Read FIFO
Table 5–5. Signals Supported by the Avalon-MM Read FIFO Block
Table 5–6. Avalon-MM Read FIFO Block Parameters
© June 2010 Altera Corporation
Stall
Data
DataValid
TestDataOut
TestDataValid Output
Ready
Data Type
[number of bits].[] >= 0
[].[number of bits] >= 0
FIFO Depth
Name
Signal
Signed Integer,
Signed Fractional,
Unsigned Integer
(Parameterizable)
(Parameterizable)
> 2
Input
Input
Input
Output
Output
Direction
The Avalon-MM Read FIFO block is essentially an Avalon-MM Slave block
configured to implement a read FIFO. It is accessed by other Avalon-MM peripherals
to obtain data when connected in SOPC Builder.
For information about the Avalon-MM Slave block, refer to
page
Table 5–5
Table 5–6
Value
5–6.
This port must be connected to Simulink blocks. It simulates stall conditions of the
Avalon-MM bus and hence back pressure to the SOPC component. For any simulation
cycle where the Stall signal is asserted, no Avalon-MM reads take place and the
internal FIFO buffer fills. When full, the Ready output is de-asserted so that no data is
lost.
This port should be connected to DSP Builder blocks and should be connected to
outgoing data from the user design.
This port should be connected to DSP Builder blocks and should be asserted whenever
the signal on the Data port corresponds to real data.
This port should be connected to Simulink blocks and corresponds to the data received
over the Avalon-MM bus.
This port should be connected to Simulink blocks and is asserted whenever
TestDataOut corresponds to real data.
lists the signals supported by the Avalon-MM Read FIFO block.
shows the Avalon-MM Read FIFO block parameters.
When asserted, indicates that the block is ready to receive data.
The number format of the bus.
Specifies the number of bits to the left of the binary point, including the sign bit.
This parameter does not apply to single-bit buses.
Specifies the number of bits to the right of the binary point. This parameter
applies only to signed fractional buses.
Specifies the depth of the FIFO.
Preliminary
Description
Description
DSP Builder Standard Blockset Libraries
“Avalon-MM Slave” on
5–9