IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 360

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

9–20
Shift Taps
Table 9–31. Shift Taps Block Parameters
Table 9–32. Shift Taps Block I/O Formats (Part 1 of 2)
DSP Builder Standard Blockset Libraries
Number of Taps
Distance Between
Taps
Use Shift Out Port On or Off
Use Enable port
Use Dedicated
Circuitry
Memory Block
Type
I
I/O
I1
I2
Name
[L1].[R1]
[1]
Simulink (2),
User Defined
(Parameterizable)
User Defined
(Parameterizable)
On or Off
On or Off
AUTO, M512, M4K,
M9K, MLAB, M144K
The Shift Taps block implements a shift register that you can use for filters or
convolution.
In Stratix IV, Stratix III, Stratix II, Stratix II GX, Stratix GX, Arria GX, Arria II GX,
Cyclone III, Cyclone II, and Cyclone devices, the block implements a RAM-based shift
register that is useful for creating very large shift registers efficiently. The block
outputs occur at regularly spaced points along the shift register (that is, taps).
In Stratix devices, this block implements in the small memory.
Table 9–30
Table 9–30. Shift Taps Block Inputs and Outputs
Table 9–31
Table 9–32
(3)
d
ena
t0–tn
sout
Value
Signal
I1: in STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0)
I2: in STD_LOGIC
shows the Shift Taps block inputs and outputs.
shows the Shift Taps block parameters.
shows the Shift Taps block I/O formats.
Specifies the number of regularly spaced taps along the shift register.
Specifies the distance between the regularly spaced taps in clock cycles, which
translates to the number of RAM words that DSP Builder uses.
Turn on to create an output from the end of the shift register for cascading.
Turn on to use an additional clock enable control input.
Turn on to enable selection of the memory block type. This option is only valid
when the Distance Between Taps is greater than 2.
The RAM block type. Some memory types are not available for all device types.
Input
Input
Output
Output
Direction
(Note 1)
Preliminary
Data input port.
Optional clock enable port.
Output ports for taps 0–n.
Optional shift out port.
VHDL
Description
Description
© June 2010 Altera Corporation
Chapter 9: Storage Library
Type
Implicit
Explicit
Shift Taps
(4)