IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 216

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

2–8
Differentiator
Table 2–14. Differentiator Block Parameters
Table 2–15. Differentiator Block I/O Formats
DSP Builder Standard Blockset Libraries
Number of Bits
Depth
Use Enable Port
Use Synchronous Clear Port On or Off
I
O
Notes to
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit.
(2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned
(3) I1
(4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath
I/O
integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit.
bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
I1
I2
I3
O1
[L].[R]
[L1].[0]
[1]
[1]
[L1].[0]
Table
Simulink (2),
is an input port. O1
Name
2–15:
(3)
The Differentiator block is a signed integer differentiator with the equation:
Use this block for DSP functions such as CIC filters.
The equation 1-z
implements.
Table 2–13
Table 2–13. Differentiator Block Inputs and Outputs
Table 2–14
Table 2–15
d
ena
sclr
q
[L].[R]
q(n) = d(n) - d(n-D)
where D is the delay parameter.
Signal
I1: in STD_LOGIC_VECTOR({L1 - 1} DOWNTO 0)
I2: in STD_LOGIC
I3: in STD_LOGIC
O1: out STD_LOGIC_VECTOR({L1 - 1} DOWNTO 0)
>= 1
(Parameterizable)
Any positive number
(Parameterizable)
On or Off
is an output port.
shows the Differentiator block inputs and outputs.
shows the Differentiator block parameters.
shows the Differentiator block I/O formats.
Value
-D
Input
Input
Input
Output
describes the transfer function that the Differentiator block
Direction
(Note 1)
Specify the number of bits.
Specify the depth of the differentiator register.
Turn on to use the clock enable input (ena).
Turn on to use the synchronous clear input (sclr).
Preliminary
Data input.
Optional clock enable.
Optional synchronous clear.
Result.
VHDL
Description
Description
© June 2010 Altera Corporation
Chapter 2: Arithmetic Library
Explicit
Explicit
Type
Differentiator
(4)