IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 326

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

6–18
Round
Table 6–30. Round Block Parameters (Part 1 of 2)
DSP Builder Standard Blockset Libraries
Bus Type
[number of bits].[]
[].[number of bits]
Number of LSB Bits
to Remove
Name
1
Signed Integer,
Signed Fractional,
Unsigned Integer
>= 2 (Parameterizable)
>= 0 (Parameterizable)
>= 0 (Parameterizable)
The Round block rounds the input to the closest possible representation in the
specified output bus format. If the nearest two possibilities are equidistant, you can
specify from the available rounding modes:
■
■
■
■
■
When using Simulink fixed-point types, MATLAB supports the following rounding
options: Zero, Nearest (equivalent to Round Away From Zero), Ceiling, Floor
(equivalent to Truncate), and Simplest. The MATLAB Zero and Ceiling modes round
all intermediate values up or down and have no DSP Builder equivalent. This is
because the DSP Builder modes (except Truncate) always specify the nearest
representable value and the rounding mode applies only to values that are equidistant
from two representable values. For example, 0.9 rounds to 1 (for all modes except
Truncate) but the MATLAB Zero mode rounds 0.9 to 0. Similarly 0.1 rounds to 0 but
the MATLAB Ceiling mode rounds 0.1 to 1.
Table 6–30
Truncate: Remove discarded bits without changing the other bits; effectively,
specify the lower value. This is the simplest and fastest mode to implement in
hardware.
Round Towards Zero: Specify the value closer to zero.
Round Away From Zero: Specify the value further from zero (round downwards
for negative values, upwards for positive values). This was the rounding behavior
in DSP Builder version 7.0 and before. When using this mode —the maximum
positive value overflows the available representation. For example, when
rounding from an 8-bit signed input to a 6-bit signed output, 01111111 (127)
becomes 100000 (-32). If you use this mode, it is best to use saturation logic to
prevent this from happening.
Round To Plus Infinity: Specify the higher value.
Convergent Rounding: Specify the even value. For a large sample of random
input values there is no bias —on average the same number of values round
upwards as downwards.
Value
shows the Round block parameters.
The number format of the bus.
Specifies the number of bits to the left of the binary point, including the
sign bit. This parameter does not apply to single-bit buses.
Specifies the number of bits to the right of the binary point. This
parameter applies only to signed fractional buses.
Specifies how many bits to remove.
Preliminary
Description
© June 2010 Altera Corporation
Chapter 6: IO & Bus Library
Round