IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 285

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 4: Gate & Control Library
Single Pulse
Table 4–38. Pattern Block Parameters (Part 2 of 2)
Table 4–39. Pattern Block I/O Formats
Figure 4–15. Pattern Block Example
Single Pulse
© June 2010 Altera Corporation
Use Enable Port
Use Synchronous Clear Port On or Off
I
O
Notes to
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit.
(2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned
(3) I1
(4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath
I/O
integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit.
bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
I1
I2
O1
[L].[R]
[1]
[1]
Simulink (2),
[1]
Table
is an input port. O1
Name
4–39:
(3)
Table 4–39
Figure 4–15
The Single Pulse block generates a single pulse output signal. The output signal is
a single bit that takes only the values 1 or 0. The signal generation type can be an
impulse, a step up (0 to 1), or a step down (1 to 0).
The output of a impulse starts at 0 changing to 1 after a specified delay and changing
to 0 again after a specified length. The output of a step up starts at 0 changing to 1
after a specified delay. The output of a step down starts at 1 changing to 0 after a
specified delay.
Table 4–40
[L].[R]
I1: in STD_LOGIC
I2: in STD_LOGIC
O1: out STD_LOGIC
On or Off
is an output port.
shows the Pattern block I/O formats.
shows the Single Pulse block inputs and outputs.
Value
shows an example with the Pattern block.
(Note 1)
Turn on to use the clock enable input (ena).
Turn on to use the synchronous clear input (sclr).
Preliminary
VHDL
Description
DSP Builder Standard Blockset Libraries
Explicit - optional
Explicit - optional
Explicit
Type
(4)
4–23