QG5000X S L9TH Intel, QG5000X S L9TH Datasheet - Page 10

• Manufacturer Part Number: QG5000X S L9TH
• Manufacturer: Intel

Specifications of QG5000X S L9TH

• Lead Free Status / RoHS Status: Compliant

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3-19 Device 5-7, Function 0: PCI Express Intel IBIST Registers .......................................64
3-20 Device 9, Function 0: AMB Switching Window Registers ..........................................64
3-21 Device 16, Function 0: Processor Bus, Boot, and Interrupt ......................................65
3-22 Device 16, Function 1: Memory Branch Map, Control, Errors ....................................66
3-23 Device 16, Function 2: RAS .................................................................................67
3-24 Device 21, 22, Function 0: FB-DIMM Map, Control, RAS ..........................................68
3-25 Device 21, Function 0: FB-DIMM 0 Intel IBIST Registers .........................................69
3-26 Device 21, Function 0: FB-DIMM 1 IBST Registers .................................................70
3-27 Device 22, Function 0: FB-DIMM 2 IBST Registers ..................................................71
3-28 Device 22, Function 0: FB-DIMM 3 Intel IBIST Registers .........................................72
3-29 Address Mapping Registers .................................................................................81
3-30 Register Offsets in AMB Memory Mapped Registers Region ......................................92
3-31 XTPR Index .......................................................................................................99
3-32 When will an Intel 5000X Chipset PCI Express* Device be Accessible? .................... 100
3-33 Intel 5000P Chipset MCH PCISTS and SECSTS Master/Data
3-1
3-34 IV Handling and Processing by MCH ................................................................... 137
3-35 Maximum Link Width Default Value for Different PCI Express Ports ......................... 147
3-36 Negotiated Link Width For Different PCI Express Ports After Training ...................... 150
3-37 Global Activation Throttling as a Function of Global Activation Throttling Limit
3-38 FB-DIMM to Host Gear Ratio Mux ....................................................................... 201
3-39 FB-DIMM to Host Gear Ratio Mux ....................................................................... 201
3-40 Host to FB-DIMM Gear Ratio Mux Select.............................................................. 202
3-41 FB-DIMM Host Data Cycle Valid Mux Select ......................................................... 203
3-42 FB-DIMM to Host Flow Control Mux Select ........................................................... 204
3-43 FB-DIMM Bubble Mux Select.............................................................................. 204
3-44 FB-DIMM to Host Double Config Mux Select ......................................................... 205
3-45 Optimum TREF values as a function of core: FBD gear ratios (in FBD Super frames) . 207
3-46 Timing Characteristics of ERRPER....................................................................... 208
3-47 Interleaving of an address is governed by MIR[i].................................................. 209
3-48 NRECFBD Mapping Information.......................................................................... 220
3-49 ECC Locator Mapping Information ...................................................................... 222
3-50 IV Vector Table for DMA Errors and Interrupts ..................................................... 263
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10 Address Disposition for Inbound Transactions ...................................................... 294
5-1
5-1
5-2
5-3
5-2
5-3
5-4
Parity Error RAS Handling ................................................................................. 113
GIO Port Mode Selection ................................................................................... 125
(GBLACTM) and Global Throttling Window Mode (GTW_MODE) Register Fields.......... 196
Memory Segments and Their Attributes .............................................................. 280
PAM Settings................................................................................................... 282
Low Memory Mapped I/O1 ................................................................................ 285
I/O APIC Address Mapping ................................................................................ 287
Intel 5000X chipset MCH Memory Mapping Registers ............................................ 289
Address Disposition for Processor....................................................................... 290
Enabled SMM Ranges ....................................................................................... 292
SMM Memory Region Access Control from Processor ............................................. 292
Decoding Processor Requests to SMM and VGA Spaces ......................................... 293
DBI[3:0]# / Data Bit Correspondence................................................................. 300
Snoop Filter Physical Address Partitioning ........................................................... 304
FSB transaction encoding qualification for SF look up............................................ 304
Snoop Filter Entry ............................................................................................ 304
Minimum System Memory Configurations & Upgrade Increments............................ 306
Maximum 16 DIMM System Memory Configurations.............................................. 307
Maximum 16 DIMM System Memory Configurations.............................................. 307
Intel® 5000X Chipset Memory Controller Hub (MCH) Datasheet