QG5000X S L9TH Intel, QG5000X S L9TH Datasheet - Page 254

• Manufacturer Part Number: QG5000X S L9TH
• Manufacturer: Intel

Specifications of QG5000X S L9TH

• Lead Free Status / RoHS Status: Compliant

254
The PCI Command register follows a subset of the PCI Local Bus Specification, Revision
2.3 specification. This register provides the basic control of the ability of the DMA
engine device to initiate and respond to transactions sent to it and maintains
compatibility with PCI configuration space.
Device:
Function:
Offset:
Version:
8
7
6
5:4
3
2
1
0
Bit
RW
RV
RW
RV
RO
RW
RW
RO
Attr
8
0
04h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
0
0
0
00
0
0
0
0
Default
SERRE:
This bit indicates whether the DMA Engine device is allowed to signal a SERR
condition.
This field handles the reporting of fatal and non-fatal errors by enabling the error
pins ERR[2:0].
1: The DMA engine device is enabled to send fatal/non-fatal errors.
0: The DMA engine device is disabled from generating fatal/non-fatal errors.
Reserved
PERRRSP:
Controls the response when a parity error is detected in the DMA engine
1: The device can report Parity errors
0: Parity errors can be ignored by the device.
Reserved
SPCEN: Special Cycle Enable
This bit does not apply to the DMA Engine Device.
BME: Bus Master Enable
Controls the ability for the DMA engine device to initiate transactions to memory
including MMIO
1: Enables the DMA engine device to successfully complete memory read/write
requests.
0: Disables
If this bit is not set and the DMA engine is programmed by software to process
descriptors, the Chipset will flag read(write) errors (*DMA8/*DMA9) and also
record the errors in the CHANERR registers when it attempts to issue cacheline
requests to memory.
MAEN: Memory Access Enable
Controls the ability for the DMA Engine Device to respond to memory mapped I/O
transactions initiated in the Intel 5000P Chipset MCH in its range.
1: Allow MMIO accesses in the DMA Engine
0: Disable MMIO accesses in DMA Engine
This only applies to access CB_BAR space in Device 8, fn 1 where the MMIO space
resides (Requests from both fast/slow paths will be master-aborted)
IOAEN: I/O Access Enable
Controls the ability for the DMA Engine Device to respond to legacy I/O
transactions. The DMA Engine Device does not support/allow legacy I/O cycles.
SERR Message Enable
upstream memory writes/reads
Parity Error Response
Intel
®
5000X Chipset Memory Controller Hub (MCH) Datasheet
Description
Register Description