QG5000X S L9TH Intel, QG5000X S L9TH Datasheet - Page 119

• Manufacturer Part Number: QG5000X S L9TH
• Manufacturer: Intel

Specifications of QG5000X S L9TH

• Lead Free Status / RoHS Status: Compliant

Register Description
3.8.8.25
3.8.8.26
3.8.8.27
Intel
®
5000X Chipset Memory Controller Hub (MCH) Datasheet
RBAR[7:2] - ROM Base Address Register
Not implemented in MCH, since the MCH is a virtual PCI-PCI bridge.
INTL[7:2,0] - Interrupt Line Register
The Interrupt Line register is used to communicate interrupt line routing information
between the initialization code and the device driver
dedicated interrupt line. This register RO and is provided for backwards compatibility
INTP[7:2,0] - Interrupt Pin Register
The INTP register identifies legacy interrupts for INTA, INTB, INTC and INTD as
determined by BIOS/firmware. These are emulated over the ESI port using the
appropriate Assert_Intx commands.
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
7:0
Bit
Attr
RO
0, 2-3
0
3Ch
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
3Ch
Intel 5000Z Chipset
4-7
0
3Ch
Intel 5000P Chipset
Default
00h
INTL: Interrupt Line
BIOS writes the interrupt routing information to this register to indicate which
input of the interrupt controller this PCI Express Port is connected to. Not used
in
MCH
since the PCI Express port does not have interrupt lines.
Description
.
The MCH does not have a
119
.