QG5000X S L9TH Intel, QG5000X S L9TH Datasheet - Page 239

• Manufacturer Part Number: QG5000X S L9TH
• Manufacturer: Intel

Specifications of QG5000X S L9TH

• Lead Free Status / RoHS Status: Compliant

Register Description
Intel
®
5000X Chipset Memory Controller Hub (MCH) Datasheet
Device:
Function: 0
Offset:
Bit
1
0
RWST
RWST
Attr
22
280h, 180h
Default
1
0
MSTRMD: Master Mode Enable
When this bit is set the next TS1 training set that has the loopback bit set will
cause the transmitter to operate as a master. Even though the Intel IBIST is in
the loopback state it is not in loopback.
0: Disable Master mode. This component will not enter into master when a TS1
training set with loopback bit set.
1: Enable Master Mode on the next TS1 training with loopback bit set
IBSTR: IBIST Start
When set, it enables receiver logic to look for start delimiters during TS1 training
set. If the MSTRMD bit is set, the start bit enables the transmit state machine to
start transmitting patterns during the TS1 training set. The receiver is enable in
both cases.
For master-slave mode, the pattern will be looped back as defined in the FB-
DIMM spec. In master-master mode, the IBIST controller will originate patterns
and also check the incoming pattern for errors.
0: Stop IBIST transmitter
1: Start IBIST transmitter
Description
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