QG5000X S L9TH Intel, QG5000X S L9TH Datasheet - Page 353

• Manufacturer Part Number: QG5000X S L9TH
• Manufacturer: Intel

Specifications of QG5000X S L9TH

• Lead Free Status / RoHS Status: Compliant

Functional Description
Figure 5-20. Intel 5000X Chipset PCI Express* High Performance x16 Port
5.13.5
Intel
®
5000X Chipset Memory Controller Hub (MCH) Datasheet
Supported Length Width Port Partitioning
To establish a connection between PCI Express endpoints, they both participate in a
sequence of steps known as training. This sequence will establish the operational width
of the link as well as adjust skews of the various lanes within a link so that the data
sample points can correctly take a data sample off of the link. In the case of a x8 port,
the x4 link pairs will first attempt to train independently, and will collapse to a single
link at the x8 width upon detection of a single device returning link ID information
upstream. Once the number of links has been established, they will negotiate to train
at the highest common width, and will step down in its supported link widths in order to
succeed in training. The ultimate result may be that the link has trained as a x1 link.
Although the bandwidth of this link size is substantially lower than a x8 link or x4 link,
it will allow communication between the two devices. Software will then be able to
interrogate the device at the other end of the link to determine why it failed to train at
a higher width.
This autonomous capability can be overridden by the values sampled on the
PEWIDTH[3:0] pins.
link widths in the PCI Express ports in the MCH.
Port 4
Table 5-4
PCI-Express cluster (IOU1)
High Performance
Transaction
Graphics Port
Port 5
illustrates the PEWIDTH strapping options for various
Physical
Link
Port 6
Port 7
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