QG5000X S L9TH Intel, QG5000X S L9TH Datasheet - Page 378

• Manufacturer Part Number: QG5000X S L9TH
• Manufacturer: Intel

Specifications of QG5000X S L9TH

• Lead Free Status / RoHS Status: Compliant

5.16.5
5.16.5.1
5.16.5.2
Figure 5-43. Random Byte Read Timing
378
FB-DIMM SPD Interface, SM Buses 1, 2, 3 and 4
The MCH integrates a 100 KHz SPD controller to access the FB-DIMM configuration
information. SMBus 1 is dedicated to FB-DIMM branch 0, channel 0 DIMMs. SMBus 2 is
dedicated to FB-DIMM branch 0, channel 1 DIMMs. SMBus 3 is dedicated to FB-DIMM
branch 1, channel 0 DIMMs and SMBus 4 is dedicated to FB-DIMM branch 1, channel 1
DIMMs. There can be a maximum of four SPD EEPROM’s associated with each SPD bus.
The FB-DIMM SPD interfaces are wired as depicted in
Board layout must map chip selects to SPD Slave Addresses as shown in
slave address is written to the SPDCMD configuration register.
SPD Asynchronous Handshake
The SPD bus is an asynchronous serial interface. Once software issues an SPD
command (SPDCMD.CMD = SPDW or SPDR), software is responsible for verifying
command completion before another SPD command can be issued. Software can
determine the status of an SPD command by observing the SPD configuration register.
An SPD command has completed when any one command completion field (RDO, WOD,
SBE) of the SPD configuration register is observed set to 1. An SPDR command has
successfully completed when the RDO field is observed set to 1. An SPDW command
has successfully completed when the WOD field is observed set to 1. An unsuccessful
command termination is observed when the SBE field is set to 1. The MCH will clear the
SPD configuration register command completion fields automatically whenever an
SPDR or SPDW command is initiated. Polling may begin immediately after initiating an
SPD command.
Software can determine when an SPD command is being performed by observing the
BUSY field of the SPD configuration register. When this configuration bit is observed set
to 1, the interface is executing a command.
Valid SPD data is stored in the DATA field of the SPD configuration register upon
successful completion of the SPDR command (indicated by 1 in the RDO field). Data to
be written by an SPDW command is placed in the DATA field of the SPDCMD
configuration register.
Unsuccessful command termination will occur when an EEPROM does not acknowledge
a packet at any of the required ACK points, resulting in the SBE field being set to 1.
Request Packet for SPD Random Read
Upon receiving the SPDR command, the MCH generates the Random Read Register
command sequence as shown in
MCH SPD configuration register in bits [7:0], and the RDO field is set to 1 by the MCH
to indicate that the data is present and that the command has completed without error.
S
T
A
R
T
D
T
3
I
Slave Address
D
T
2
I
D
T
1
I
D
T
0
I
S
A
2
S
A
1
S
A
0
W
R
/
A
C
K
0
B
A
7
B
A
6
Byte Address
B
A
5
B
A
4
B
A
3
Figure
B
A
2
A
B
1
Intel
B
A
0
5-43. The returned data is then stored in the
A
C
K
®
R
S
T
A
T
5000X Chipset Memory Controller Hub (MCH) Datasheet
D
T
3
I
Slave Address
D
T
2
I
D
T
1
I
D
T
0
I
S
A
2
Figure
S
A
1
S
A
0
W
R
/
A
C
K
5-8.
1
Functional Description
DATA
Table
5-7. The
N
A
C
K
O
S
T
P