QG5000X S L9TH Intel, QG5000X S L9TH Datasheet - Page 81

• Manufacturer Part Number: QG5000X S L9TH
• Manufacturer: Intel

Specifications of QG5000X S L9TH

• Lead Free Status / RoHS Status: Compliant

Register Description
3.8.1.7
3.8.2
Table 3-29. Address Mapping Registers
Intel
®
5000X Chipset Memory Controller Hub (MCH) Datasheet
SID - Subsystem Identity
This register identifies the system. They appear in every function except the PCI
Express functions.
Address Mapping Registers
These registers control transaction routing to one of the three interface types (Memory,
PCI Express, or ESI) based on transaction addresses. The memory mapping registers in
this section are made read-only by the LT.LOCK-MEMCONFIG command. Routing to
particular ports of a given interface type are defined by the following registers:
1. Any request not falling in the above ranges will be subtractively decoded and sent to Intel 631xESB/632xESB
The MCH allows programmable memory attributes on 13 Legacy memory segments of
various sizes in the 640 Kilobytes to 1 Megabytes address range. Seven Programmable
Attribute Map (PAM) Registers are used to support these features.
Notes:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
15:0
Memory
PCI Express
ESI
Bit
Interface
I/O Controller Hub via the ESI
type
RWO
Attr
0, 8
0
2Eh
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
16
0, 2
2Eh
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
17
0
2Eh
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
21
0
2Eh
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
22
0
2Eh
Intel 5000P Chipset
8086h
MIR, AMIR, PAM, SMRAM, EXSMRC, EXSMRAMC, TOLM, EXSMRTOP, AMBASE, AMR
MBASE/MLIM (devices 2-7)
PMBASE/PMLIM (devices 2-7)
PMBU/PMBL (devices 2-7)
IOBASE/IOLIM (devices 2-7)
SBUSN,SUBUSN (devices 2-7)
BCTRL, HECBASE, PCICMD (devices 2-7)
Subtractive decode
Default
Subsystem Identification Number:
The default value specifies Intel. Each byte of this register will be writable once.
Second and successive writes to a byte will have no effect.
1
(device 0)
Address Routing Registers
Description
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