QG5000X S L9TH Intel, QG5000X S L9TH Datasheet - Page 315

• Manufacturer Part Number: QG5000X S L9TH
• Manufacturer: Intel

Specifications of QG5000X S L9TH

• Lead Free Status / RoHS Status: Compliant

Functional Description
5.3.6
5.3.7
5.3.7.1
5.3.7.2
Intel
®
5000X Chipset Memory Controller Hub (MCH) Datasheet
Demand Scrubbing
To enable this function, the MC.DEMSEN configuration bit must be set. Correctable read
data will be corrected to the requestor and scrubbed in memory. This adds an extra
cycle of latency to accomplish the correction. Error logs include RAS/CAS/BANK/RANK.
Demand scrubbing is not available in mirrored mode (when MC.MIRROR is set) to
simplify the design. If a correctable error is encountered, the data is corrected and sent
to the requestor at the cost of one extra cycle of latency. The probability of soft errors
due to alpha rays affecting multiple x4/x8 devices is low. However, patrol scrubbing
when enabled in the Intel 5000P Chipset MCH for the Mirrored mode will clean up all
correctable errors in the memory running in the background and runs twice as fast.
There is no incurred RAS benefit by enforcing demand scrubbing in mirrored mode with
the exception of the error logging. Demand scrubbing does not help in failed ECC case
(uncorrectable errors). That is, If the data read is uncorrectable from the bad branch,
then the golden data needs to be retrieved from the other mirrored branch (copy) at
the cost of additional FB-DIMM reset, link training and DDR protocol rules. The failed
branch is offlined and needs to be replaced for mirroring to continue.
x8 Correction
Normal
This correction mode is in effect when the MC.SCRBALGO configuration bit is cleared.
An erroneous read will be logged. If the ECC was correctable, it is corrected (scrubbed)
in memory. A conflicting read or write request pending issue will be held until the scrub
is either completed or aborted because it was uncorrectable.
Enhanced
This correction mode is in effect when the MC.SCRBALGO configuration bit is set and
software has initialized the MC.BADRAMTH to a non-zero value.
Floor at zero. Saturate at the value of the MC.BADRAMTH configuration register field.
Increment on correctable errors on both symbols of a x8 device and Northbound CRC
OK. Decrement upon completion of the number of patrol scrub cycles through the
entire memory specified by the MC.BADRAMTH configuration register field. A sufficient
resolution of this period is three patrol scrub cycles through all memory.
Upon incrementing BADCNT to saturation, then mark the bad devices in the
BADRAM(A/B) configuration registers.
An erroneous read will be logged. If the read was correctable, it is corrected (scrubbed)
in memory. A conflicting read or write request remains pending until the scrub
succeeds or is dropped. A failed scrub is replayed once, resulting in success or a drop.
• Maintain 4-bit saturating counters per rank in the BADCNT configuration registers.
• Maintain five-bit bad-device marks per rank in the BADRAM(A/B) configuration
• A correctable ECC in a symbol other than that marked in the BADRAM(A/B)
registers.
configuration registers is an aliased uncorrectable read.
315