QG5000X S L9TH Intel, QG5000X S L9TH Datasheet - Page 250

• Manufacturer Part Number: QG5000X S L9TH
• Manufacturer: Intel

Specifications of QG5000X S L9TH

• Lead Free Status / RoHS Status: Compliant

3.9.25.19
3.9.25.20
3.9.25.21
3.9.25.22
250
FBD[3:2]IBPATBUF2: FB-DIMM Intel IBIST Pattern Buffer 2 Register
This register contains the pattern bits used in Intel IBIST operations.
FBD[1:0]IBPATBUF2: FB-DIMM Intel IBIST Pattern Buffer 2 Register
This register contains the pattern bits used in Intel IBIST operations.
FBD[3:2]IBTXPAT2EN: Intel IBIST TX Pattern Buffer 2 Enable
This register enables which channels are inverted when Intel IBIST operations are
activated.
FBD[1:0]IBTXPAT2EN: Intel IBIST TX Pattern Buffer 2 Enable
This register enables which channels are inverted when Intel IBIST operations are
activated.
Device:
Function: 0
Offset:
31:24
23:0
Device:
Function: 0
Offset:
31:24
23:0
Device:
Function: 0
Offset:
31:14
13:10
9:0
Bit
Bit
Bit
RV
RWST
RV
RWST
RWST
RWST
Attr
Attr
Attr
RV
22
2A4h, 1A4h
21
2A4h, 1A4h
22
2A8h, 1A8h
0
02CCFDh
0
02CCFDh
Default
Default
Default
3FFh
0h
Fh
Reserved
txpatt2hvmen: receiver Pattern Buffer 2 Enable for the HVM lanes
Selects which channels to enable the second pattern buffer.
txpatt2en: receiver Pattern Buffer 2 Enable
Selects which channels to enable the second pattern buffer.
Reserved
IBPATBUF: Intel IBIST Pattern Buffer
Pattern buffer storing the default and the user programmable pattern.
Default: 0000_0010_1100_1100_1111_1101
Reserved
IBPATBUF: Intel IBIST Pattern Buffer
Pattern buffer storing the default and the user programmable pattern.
Default: 0000_0010_1100_1100_1111_1101
Intel
®
5000X Chipset Memory Controller Hub (MCH) Datasheet
Description
Description
Description
Register Description