QG5000X S L9TH Intel, QG5000X S L9TH Datasheet - Page 289

• Manufacturer Part Number: QG5000X S L9TH
• Manufacturer: Intel

Specifications of QG5000X S L9TH

• Lead Free Status / RoHS Status: Compliant

System Address Map
4.3.9
4.3.9.1
4.3.9.2
4.4
4.4.1
Table 4-5.
Intel
®
5000X Chipset Memory Controller Hub (MCH) Datasheet
Main Memory Region
Application of Coherency Protocol
The Intel 5000X chipset MCH applies the coherency protocol to all accesses to main
memory. Application of the coherency protocol includes snooping the other processor
bus.
Two exceptions to this rule are the Expansion Card BIOS area, 0C 0000h - 0F FFFFh
and the legacy SMM, 0A 0000h - 0B FFFFh, range. The Expansion Card BIOS area 0C
0000h - 0F FFFFh may not necessarily route both reads and writes to memory, the
legacy SMM range, 0A 0000h - 0B FFFFh, may target non-memory when not in SMM
mode. The coherency protocol is not applied to these two exceptions.
Routing Memory Requests
When a request appears on the processor bus, ESI port, or PCI Express link, and it
does not fall in any of the previously mentioned regions, it is compared against the
MIR.LIMIT registers in the MCH.
The Intel 5000P Chipset MCH.MIR.LIMIT registers will decode an access into a specific
interleaving range. Within the interleaving range, the Intel 5000P Chipset
MCH.MIR.LIMIT register indicates which FB-DIMM memory branch the address is
associated with. In the event that a mirroring event is occurring, memory writes are
associated with both FB-DIMM branches.
Memory Address Disposition
The following section presents a summary of address dispositions for the Intel 5000X
chipset MCH.
Registers Used for Address Routing
Table 4-5
These registers are described in detail in
Intel 5000X chipset
EXSMRC, EXSMRAMC
MBASE (dev 2-7)
EXSMRTOP
AMIR[2:0]
PAM[6:0]
HECBASE
MIR[2:0]
SMRAMC
Name
BCTRL
TOLM
is a summary of the registers used to control memory address disposition.
Memory Interleaving Registers (FB-DIMM Branch Interleaving)
Scratch pad register for software to use related to memory interleaving. For
example, software can write MMIO gap adjusted limits here to aid in subsequent
memory RAS operations.
Defines attributes for ranges in the C and D segments. Supports shadowing by
routing reads and writes to memory of I/O.
SMM Control
Extended SMM Control
Top of extended SMM memory
Contains VGAEN and ISAEN for each PCI Express.
Top of low memory. Everything between TOLM and 4 GB will not be sent to
memory.
Base of the memory mapped configuration region that maps to all PCI Express
registers.
Base address for memory mapped I/O to PCI Express ports 2 - 7.
MCH Memory Mapping Registers (Sheet 1 of 2)
Section
3.
Function
289