QG5000X S L9TH Intel, QG5000X S L9TH Datasheet - Page 110

• Manufacturer Part Number: QG5000X S L9TH
• Manufacturer: Intel

Specifications of QG5000X S L9TH

• Lead Free Status / RoHS Status: Compliant

3.8.8.11
3.8.8.12
3.8.8.13
110
SUBUSN[7:2] - Subordinate Bus Number
This register identifies the subordinate bus (if any) that resides at the level below the
secondary PCI Express interface. This number is programmed by the PCI configuration
software to allow mapping of configuration cycles to devices subordinate to the
secondary PCI Express port.
SEC_LT[7:2] - Secondary Latency Timer
This register denotes the maximum time slice for a burst transaction in legacy PCI 2.3
on the secondary interface. It does not affect/influence PCI Express functionality.
IOBASE[7:2] - I/O Base Register
The I/O Base and I/O Limit registers (see
that is used by the PCI Express port to determine when to forward I/O transactions
from one interface to the other using the following formula:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
7:0
7:0
Bit
Bit
Attr
Attr
RW
RO
2-3
0
1Ah
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
1Ah
Intel 5000Z Chipset
4-7
0
1Ah
Intel 5000P Chipset
2-3
0
1Bh
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
1Bh
Intel 5000Z Chipset
4-7
0
1Bh
Intel 5000P Chipset
Default
Default
00h
00h
SUBBUSNUM: Subordinate Bus Number
This register is programmed by configuration software with the number of the
highest subordinate bus that is behind the PCI Express port.
Slat_tmr: Secondary Latency Timer
Not applicable to PCI Express. Hardwired to 00h.
IO_BASE <= A[15:12]<=IO_LIMIT
Intel
®
Section
5000X Chipset Memory Controller Hub (MCH) Datasheet
3.8.8.14) define an address range
Description
Description
Register Description