QG5000X S L9TH Intel, QG5000X S L9TH Datasheet - Page 142

• Manufacturer Part Number: QG5000X S L9TH
• Manufacturer: Intel

Specifications of QG5000X S L9TH

• Lead Free Status / RoHS Status: Compliant

3.8.11.4
142
PEXDEVCTRL[7:2, 0] - PCI Express Device Control Register
The PCI Express Device Control register controls PCI Express specific capabilities
parameters associated with this port.
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
14:12
Bit
15
11
10
RWST
Attr
RW
RW
RV
0, 2-3
0
74h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
74h
Intel 5000Z Chipset
4-7
0
74h
Intel 5000P Chipset
Default
101
0h
1
0
Reserved.
MRRS: Max_Read_Request_Size
This field sets maximum Read Request size generated by the
Chipset MCH
size exceeding the set value.
000: 128B max read request size
001: 256B max read request size
010: 512B max read request size
011: 1024B max read request size
100: 2048B max read request size
101: 4096B max read request size
110: Reserved
111: Reserved
The MCH will not generate read requests larger than 64B in general on the
outbound side due to the internal Micro-architecture (CPU initiated, DMA or
Peer to Peer). Hence the field is set to 000b encoding.
ENNOSNP: Enable No Snoop
When set, the PCI Express port is permitted to set the “No Snoop bit” in the
Requester Attributes of transactions it initiates that do not require hardware
enforced cache coherency. Typically the “No Snoop bit” is set by an
originating PCI Express device down in the hierarchy.
The
received TLP even if ENNOSNP is enabled. For outbound traffic, the
5000P Chipset MCH
APPME: Auxiliary Power Management Enable
1: Enables the PCI Express port to draw AUX power independent of PME
AUX power.
0: Disables the PCI Express port to draw AUX power independent of PME
AUX power.
Devices that require AUX power on legacy operating systems should
continue to indicate PME AUX power requirements. AUX power is allocated
as requested in the AUX_Current field on the Power Management
Capabilities Register (PMC), independent of the PMEEN bit in the Power
Management.
Control & Status Register (PMCSR) defined in
Intel 5000P Chipset MCH
. The PCI Express port must not generate read requests with
Intel
®
does not need to snoop.
5000X Chipset Memory Controller Hub (MCH) Datasheet
never sets or modifies the “No snoop bit” in the
Description
Section 3.8.9.2
Register Description
.
Intel 5000P
Intel