QG5000X S L9TH Intel, QG5000X S L9TH Datasheet - Page 270

• Manufacturer Part Number: QG5000X S L9TH
• Manufacturer: Intel

Specifications of QG5000X S L9TH

• Lead Free Status / RoHS Status: Compliant

3.11.5
270
PEX[7:2,0]IBSYMBUF: PEX Intel IBIST Symbol Buffer
This register contains the character symbols that are transmitted on the link. Only valid
PCI Express control characters/symbols are allowed for Intel IBIST testing.
Device:
Function: 0
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function: 0
Offset:
Version:
6:4
Bit
7
3
2
1
0
3-2, 0
380h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
7-4
380h
Intel 5000P Chipset
Attr
RW
RW
RW
RW
RW
RV
4-5
0
380h
Intel 5000Z Chipset
Default
000
0
1
0
0
0
SUPSKP: Suppress Skips
0: Skips are still inserted in the Intel IBIST data stream during Intel IBIST test
operations.
1: Skip insertion is suppressed
DSYMINJLNUM: Delay Symbol Injection Lane Number
This selects the Lane number to inject the delay symbol pattern. All 8 values
could be valid depending on the setting of the IBEXTCTL.LNMODUEN bit field.
This is true regardless of whether this Intel IBIST engine is instantiated for a
x4 or a x8 port.
AUTOSEQEN: Automatic Sequencing Enable of Delay Symbol
0: Disable delay symbol auto-sequence. Intel IBIST does not automatically
sequence the delay symbol across the width of the link.
1: Enable delay symbol auto-sequencing.
Reserved
INITDISP: Initial Disparity
This bit sets the disparity of the first Intel IBIST data pattern symbol. The
default is negative meaning that the first symbol transmitted by Tx will have a
negative disparity regardless of what the running disparity is. This allows a
deterministic pattern set to be transmitted on the link for every Intel IBIST
run. If Intel IBIST causes a discontinuous disparity error in the receiver this
error can be ignored in the reporting register. It will not affect the operation of
the Intel IBIST since it is outside of its domain. Higher levels of software
management must be aware that side effects from running Intel IBIST could
cause other errors and should they be ignored.
0: Disparity starts as negative
1: Disparity starts as positive
IBSTR: Intel IBIST Start
This bit is OR’ed with the global start bit.
0: Stop Intel IBIST
1: Start Intel IBIST
Intel
®
5000X Chipset Memory Controller Hub (MCH) Datasheet
Description
Register Description