QG5000X S L9TH Intel, QG5000X S L9TH Datasheet - Page 184

• Manufacturer Part Number: QG5000X S L9TH
• Manufacturer: Intel

Specifications of QG5000X S L9TH

• Lead Free Status / RoHS Status: Compliant

3.8.13.3
3.8.13.4
3.8.13.5
.
3.8.13.6
184
FERR_FAT_FSB[1:0]: FSB First Fatal Error Register
FERR_NF_FSB[1:0]: FSB First Non-Fatal Error Register
NERR_FAT_FSB[1:0]: FSB Next Fatal Error Register
This register logs all FSB subsequent errors after the FERR_FAT_FSB has logged the 1st
fatal error.
NERR_NF_FSB[1:0]: FSB Next Non-Fatal Error Register
This register logs all FSB subsequent errors after the FERR_NF_FSB has logged the 1st
fatal error.
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
7:6
2:1
7:3
7:6
2:1
Bit
Bit
Bit
5
4
3
0
2
1
0
5
4
3
0
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
Attr
Attr
Attr
RV
RV
RV
RV
RV
RV
RV
16
0
480h, 180h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
16
0
481h, 181h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
16
0
482h, 182h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Default
Default
Default
00000
00
0h
0h
00
0h
0
0
0
0h
0
0
0
0
0
0
Reserved
F7Err: Detected MCERR from a processor
F8Err: Detected BINIT from a processor
F6Err: Parity Error in Data from FSB Interface
Reserved
F9Err: FSB protocol Error
Reserved
F2Err: Unsupported Processor Bus Transaction
Reserved
F1Err: Request/Address Parity Error
Reserved
F9Err: FSB protocol Error
Reserved
F2Err: Unsupported Processor Bus Transaction
Reserved
F1Err: Request/Address Parity Error
Intel
®
5000X Chipset Memory Controller Hub (MCH) Datasheet
Description
Description
Description
Register Description