QG5000X S L9TH Intel, QG5000X S L9TH Datasheet - Page 251

• Manufacturer Part Number: QG5000X S L9TH
• Manufacturer: Intel

Specifications of QG5000X S L9TH

• Lead Free Status / RoHS Status: Compliant

Register Description
3.9.25.23
3.9.25.24
Intel
®
5000X Chipset Memory Controller Hub (MCH) Datasheet
FBD[3:2]IBRXPAT2EN: Intel IBIST RX Pattern Buffer 2 Enable
This register enables inversion pattern testing on individual lanes.
FBD[1:0]IBRXPAT2EN: Intel IBIST RX Pattern Buffer 2 Enable
This register enables inversion pattern testing on individual lanes.
Device:
Function: 0
Offset:
Device:
Function: 0
Offset:
Device:
Function: 0
Offset:
31:14
13:10
31:14
31:14
13:0
13:0
9:0
Bit
Bit
Bit
RWST
RWST
RWST
RWST
Attr
Attr
Attr
RV
RV
RV
21
22
2ACh, 1ACh
21
2ACh, 1ACh
2A8h, 1A8h
Default
Default
Default
3FFFh
3FFFh
3FFh
0h
Fh
0h
0h
Reserved
txpatt2hvmen: receiver Pattern Buffer 2 Enable for the HVM lanes
Selects which channels to enable the second pattern buffer.
txpatt2en: receiver Pattern Buffer 2 Enable
Selects which channels to enable the second pattern buffer.
Reserved
rxpatt2en: Receiver Pattern Buffer 2 Enable
Selects which channels to enable the second pattern buffer.
Reserved
rxpatt2en: Receiver Pattern Buffer 2 Enable
Selects which channels to enable the second pattern buffer.
Description
Description
Description
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