QG5000X S L9TH Intel, QG5000X S L9TH Datasheet - Page 50
QG5000X S L9TH
Manufacturer Part Number
QG5000X S L9TH
Description
Manufacturer
Intel
Datasheet
1.QG5000X_S_L9TH.pdf
(458 pages)
Specifications of QG5000X S L9TH
Lead Free Status / RoHS Status
Compliant
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3.4.2
Table 3-3.
50
Special Device and Function Routing
All devices in the Intel® 5000X chipset MCH reside on Bus 0. The following table
describes the devices and functions that the MCH implements or routes specially. The
DIMM component designator consists of a three-digit code: the first digit is the branch,
the second digit is the channel on the branch, and the third digit is the DIMM (FB-DIMM
command “DS” field) on the channel.
Functions Specially Handled by the MCH
To comply with the PCI specification, accesses to non-existent functions, registers, and
bits will be master aborted. This behavior is defined in the following table:
MCH
MCH
MCH
MCH
MCH
MCH
MCH
MCH
MCH
MCH
MCH
DIMM
MCH
MCH
MCH
MCH
MCH
MCH
Component
PCI Express Port 2
PCI Express Port 3
PCI Express Port 4
PCI Express Port 5
PCI Express Port 6
PCI Express Port 7
DMA Engine
DMA Engine MMIO Space
Memory Map, Error Flag/Mask,
RAS, Channel Control for FB-
DIMM Branch 0
Memory Map, Error Flag/Mask,
RAS, Channel Control for FB-
DIMM Branch 1
Processor Bus, Boot, Interrupt,
System Address
AMB Memory Mapped registers
Address Mapping, Memory
Control, Error Logs
FSB Error Registers
PCI Express Port 2-3
PCI Express Port 4-5
PCI Express Port 6-7
PCI Express Port 4-7
Register Group
Intel
25E2h
25E3h
25E4h
25E5h
25E6h
25E7h
1A38h
N/A
25F5h
25F6h
25F0h
N/A
25F0h
25F0h
25F7h
25F8h
25F9h
25FAh
®
DID
5000X Chipset Memory Controller Hub (MCH) Datasheet
2
3
4
5
6
7
8
8
21
22
16
9
16
16
2
4
6
4
Device
0
0
0
0
0
0
0
1
0
0
0
0
1
2
0
0
0
0
Functio
n
Depending on what is
connected to these
ports, some may not be
accessible.
New device mapping for
DMA Engine
Debug and DFT in
higher address offsets.
Debug and DFT in
higher address offsets.
Debug and DFT in
higher address offsets.
Route out to AMB per
AMBSELECT register
only for JTAG/SMBus.
Debug and DFT in
higher address offsets.
x8 mode. Only port 2 is
active
x8 mode. Only port 4 is
active
x8 mode. Only port 6 is
active
x16 mode. Only port 4
is active
Register Description
Comment
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