QG5000X S L9TH Intel, QG5000X S L9TH Datasheet - Page 188

• Manufacturer Part Number: QG5000X S L9TH
• Manufacturer: Intel

Specifications of QG5000X S L9TH

• Lead Free Status / RoHS Status: Compliant

3.8.13.15
188
MCERR_FSB[1:0]: FSB MCERR Mask Register
This register enables the signaling of MCERR when an error flag is set. Note that one
and only one error signal should be enabled ERR2_FSB, ERR1_FSB, ERR0_FSB, and
MCERR_FSB for each of the corresponding bits.
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
15:9
15:9
Bit
Bit
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
Attr
Attr
RV
RV
RV
RV
RV
RV
RV
RV
16
0
494h, 194h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
16
0
49Ah, 19Ah
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Default
Default
0h
0h
0h
0h
1
1
1
1
1
1
0h
0h
0h
0h
1
1
1
1
1
1
Reserved
F9Msk: FSB Protocol Error
F8Msk: B-INIT
F7Msk: Detected MCERR
F6Msk: Data Parity Error
Reserved
Reserved
Reserved
F2Msk: Unsupported Processor Bus Transaction
F1Msk: Request/Address Parity Error
Reserved
F9Msk: FSB Protocol Error
F8Msk: B-INIT
F7Msk: Detected MCERR
F6Msk: Data Parity Error
Reserved
Reserved
Reserved
F2Msk: Unsupported Processor Bus Transaction
F1Msk: Request/Address Parity Error
Intel
®
5000X Chipset Memory Controller Hub (MCH) Datasheet
Description
Description
Register Description