QG5000X S L9TH Intel, QG5000X S L9TH Datasheet - Page 343

• Manufacturer Part Number: QG5000X S L9TH
• Manufacturer: Intel

Specifications of QG5000X S L9TH

• Lead Free Status / RoHS Status: Compliant

Functional Description
Figure 5-15. PCI Express Hot-Plug Interrupt Flow
Intel
®
5000X Chipset Memory Controller Hub (MCH) Datasheet
4. PCI Hot-Plug - Chipset will receive an Assert/Deassert GPE message from the PCI
5. PCI Express Power management - PCI Express sends a PME message. Chipset
Express port when a PCI Hot-Plug event is happening. Assert/Deassert GPE
messages should be treated the same as Assert/Deassert GPE messages for PCI
Express Hot-Plug. (Keep track of Assert/Deassert GPE messages from each port
and send Assert_GPE, Deassert_GPE message to ESI appropriately)
sends Assert_PMEGPE to ESI port when a power management event is detected.
a. Upon receipt of the PME message, Intel 5000X chipset MCH will set the
HPGPEEN
PEXRTSTS.PMESTATUS bit corresponding to that port and send Assert_PMEGPE
to ESI port to generate the interrupt. (Assert_PMEGPE should be sent if one or
more of the PMESTATUS bits are set and enabled.) To generate an SCI (ACPI),
this message will be used by the Intel 631xESB/632xESB I/O Controller Hub to
drive appropriate pin. When software has completed servicing the power
1
0
0
0
0
PEXSLOTCTRL[x].
(PEXCTRL.HPGPE
PEXCMD[x].INTx
HPINTEN = 1?
MSIEN == 1) ?
Disable == 1?
(MSICTRL[x].
PEXHPINT
EN == 1)
N
Y
N
Y
HPINTEN
1
1
1
0
x
Y
Y
N
N
Intel® 5000P Chipset
Intel® 5000P Chipset
Sends assert_INTx
Sends assert_HPGPE
Intel® 5000P Chipset
message via DMI
per MSIAR and
message via DMI
per INTP
sends MSI
MSIEN
SW polls
MSIDR
status
x
1
0
0
x
INTx Disable
Intel® 5000P Chipset
Sends desassert_INTx
sends desassert_HPGP
PEXSLOTSTS str
message via DMI
Intel® 5000P Chipset
respective bits of
cleared (wired-
PEXSLOTSTS str
E message via
respective bits of
DMI when the
cleared (wired-
when the
0
1
x
x
x
OR)
OR)
assert_hpgpe
assert_intx
Output
MSI
--
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