QG5000X S L9TH Intel, QG5000X S L9TH Datasheet - Page 91

• Manufacturer Part Number: QG5000X S L9TH
• Manufacturer: Intel

Specifications of QG5000X S L9TH

• Lead Free Status / RoHS Status: Compliant

Register Description
3.8.3.2
3.8.3.3
3.8.3.4
3.8.3.5
Intel
®
5000X Chipset Memory Controller Hub (MCH) Datasheet
AMR - AMB Memory Mapped Registers Region Range Register
AMBSELECT - AMB Switching Window Select Register
MAXCH - Maximum Channel Number Register
MAXDIMMPERCH - Maximum DIMM PER Channel Number Register
This register controls the maximum number of AMB DIMMs per FB-DIMM channel that
MCH supports for AMB configuration register access. This register applies only to DIMM
modules in the FB-DIMM channel, that is, those AMB with DS[3:0] encoding from 0h
to 7h.
Device:
Function:
Offset:
Version:
31:0
Device:
Function:
Offset:
Version:
15:9
8:7
6:3
2:0
Device:
Function:
Offset:
Version:
Bit
Bit
7:0
Bit
RV
RW
RW
RW
RW
Attr
Attr
Attr
RO
16
0
50h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
16
0
54h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
16
0
56h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset,
0002_0000h AMBASE_Region_Size:
0h
0h
0h
0h
Default
Default
Default
04h
The size of AMB memory mapped register region in bytes. For MCH, the value
is 128 KB: 2 KB per AMB for a total of 16 AMB per channel, 32 KB per FB-DIMM
channel for a total of four channels.
Reserved
Channel_Select:
Specify the FB-DIMM channel being accessed via bus 0, device 9, function 0 for
SM Bus and JTAG only.
AMB_Select:
Specify the AMB slot being accessed via bus 0, device 9, function 0 for SM Bus
and JTAG only.
Function_Select:
Specify the function being accessed via bus 0, device 9, function 0 for SM Bus
and JTAG only.
Maximum_number_channels:
Set by hardware to indicate the maximum number of FB-DIMM channels that
MCH supports.
Description
Description
Description
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