QG5000X S L9TH Intel, QG5000X S L9TH Datasheet - Page 51

• Manufacturer Part Number: QG5000X S L9TH
• Manufacturer: Intel

Specifications of QG5000X S L9TH

• Lead Free Status / RoHS Status: Compliant

Register Description
Table 3-4.
3.5
3.5.1
Table 3-5.
Intel
®
5000X Chipset Memory Controller Hub (MCH) Datasheet
Access to “Non-Existent” Register Bits
I/O Mapped Registers
There are only two I/O addresses that affect the Intel 5000X MCH state. The first
address is the DWORD location (CF8h) references a read/write register that is named
CONFIG_ADDRESS. The second DWORD address (CFCh) references a read/write
register named CONFIG_DATA. These two addresses are used for the PCI CFCh / CF8h
configuration access mechanism.
CFGADR: Configuration Address Register
CFGADR is written only when a processor I/O transaction to I/O location CF8h is
referenced as a DWord; a Byte or Word reference will not access this register, but will
generate an I/O space access. Therefor the only I/O space taken up by this register is
the DWORD at location CF8h. I/O devices that share the same address but use BYTE or
WORD registers are not affected because their transactions will pass through the host
bridge unchanged.
The CFGADR register contains the Bus Number, Device Number, Function Number, and
Register Offset for which a subsequent CFGDAT access is intended. The mapping
between fields in this register and PCI Express configuration transactions is defined by
Table
I/O Address: CF8h
Devices listed in
ESI Device Identification” on page 49
functions not listed
Devices listed in
ESI Device Identification” on page 49,
registers not listed in
Definitions.”
Reserved bits in registers
30:24
23:16
15:11
10:8
7:2
1:0
Bit
31
3-1.
Attr
RW
RW
RW
RW
RW
RW
RV
Table 3-2, “Memory Control Hub
Table 3-2, “Memory Control Hub
Default
Access to
SSection 3.8, “Register
00h
00h
00h
0h
0h
0h
0h
CFGE: Configuration Enable
Unless this bit is set, accesses to the CFGDAT register will not produce a
configuration access, but will be treated as other I/O accesses. This bit is
strictly an enable for the CFC/CF8 access mechanism and is not forwarded to
ESI or PCI Express.
Reserved.
Bus Number
If 0, the MCH examines device to determine where to route. If non-zero, route
as per PBUSN and SBUSN registers.
Device Number
This field is used to select one of the 32 possible devices per bus.
Function Number
This field is used to select the function of a locally addressed register.
Register Offset
If this register specifies an access to MCH registers, this field specifies a group
of four bytes to be addressed. The bytes accessed are defined by the Byte
enables of the CFGDAT register access
Writes to these bits have no effect, reads return 0
but to
but to
Have no effect
Have no effect
Software must read-
modify-write to preserve
the value
Writes
Description
MCH returns all zeroes
MCH returns all zeroes
MCH returns all ones
Reads
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