QG5000X S L9TH Intel, QG5000X S L9TH Datasheet - Page 132

• Manufacturer Part Number: QG5000X S L9TH
• Manufacturer: Intel

Specifications of QG5000X S L9TH

• Lead Free Status / RoHS Status: Compliant

3.8.9.2
132
PMCSR[7:2, 0] - Power Management Control and Status Register
This register provides status and control information for PM events in the PCI Express
port of the MCH.
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
31:27
24:22
18:16
15:8
7:0
Bit
26
25
21
20
19
Attr
RO
RO
RO
RO
RO
RO
RO
RO
RO
RV
0, 2-3
0
50h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
50h
Intel 5000Z Chipset
4-7
0
50h
Intel 5000P Chipset
Default
11001
010
58h
01h
0h
0
0
0
0
0
PMES: PME Support
Identifies power states in the Intel 5000P Chipset MCH which can send an
“Assert_PMEGPE/Deassert PMEGPE” message. Bits 31, 30 and 27 must be set
to '1' for PCI-PCI bridge structures representing ports on root complexes. The
definition of these bits is taken from the PCI Bus Power Management Interface
Specification Revision 1.1.
XXXX1b - Assert_
XXX1Xb - Assert_
supported by Intel 5000P Chipset MCH)
XX1XXb - Assert_
supported by Intel 5000P Chipset MCH)
X1XXXb - Assert_
(Supported by Intel 5000P Chipset MCH)
1XXXXb - Assert_
(Not supported by Intel 5000P Chipset MCH)
D2S: D2 Support
Intel 5000P Chipset MCH
D1S: D1 Support
Intel 5000P Chipset MCH
AUXCUR: AUX Current
DSI: Device Specific Initialization
Reserved.
PMECLK: PME Clock
This field is hardwired to 0h as it does not apply to PCI Express.
VER: Version
This field is set to 2h as version number from the PCI Express Base
Specification
NXTCAPPTR: Next Capability Pointer
This field is set to offset 58h for the next capability structure (MSI) in the PCI
2.3 compatible space.
CAPID: Capability ID
Provides the PM capability ID assigned by PCI-SIG.
, Revision 1.0a
Intel
PMEGPE
PMEGPE/Deassert PMEGPE
PMEGPE/Deassert PMEGPE
PMEGPE/Deassert PMEGPE
PMEGPE/Deassert PMEGPE
®
5000X Chipset Memory Controller Hub (MCH) Datasheet
does not support power management state D2.
does not support power management state D1.
/
Deassert PMEGPE
specification.
Description
can be sent from D1 (Not
can be sent from D2 (Not
can be sent from D3 hot
can be sent from D3 cold
can be sent from D0
Register Description