QG5000X S L9TH Intel, QG5000X S L9TH Datasheet - Page 7

• Manufacturer Part Number: QG5000X S L9TH
• Manufacturer: Intel

Specifications of QG5000X S L9TH

• Lead Free Status / RoHS Status: Compliant

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Intel® 5000X Chipset Memory Controller Hub (MCH) Datasheet
5.17
5.18
Testability ............................................................................................................. 395
6.1
6.2
Electrical Characteristics ....................................................................................... 405
7.1
7.2
Ballout and Package Information........................................................................... 413
8.1
8.2
1-1
2-1
2-2
2-3
2-4
2-5
5.16.1 Internal Access Mechanism .................................................................... 367
5.16.2 SMBus Transaction Field Definitions ........................................................ 368
5.16.3 SMB Transaction Pictographs ................................................................. 371
5.16.4 Slave SM Bus, SM Bus 0........................................................................ 373
5.16.5 FB-DIMM SPD Interface, SM Buses 1, 2, 3 and 4 ...................................... 378
5.16.6 PCI Express Hot-Plug Support, SM Bus 6 ................................................. 379
5.16.7 Hot-Plug Controller ............................................................................... 380
5.16.8 PCI Express Hot-Plug Usage Model.......................................................... 380
5.16.9 Virtual Pin Ports ................................................................................... 381
Clocking......................................................................................................... 384
5.17.1 Reference Clocks.................................................................................. 384
5.17.2 JTAG .................................................................................................. 386
5.17.3 SMBus Clock........................................................................................ 386
5.17.4 GPIO Serial Bus Clock ........................................................................... 386
5.17.5 Clock Pins ........................................................................................... 386
5.17.6 High Frequency Clocking Support ........................................................... 387
Error List........................................................................................................ 388
JTAG Port ....................................................................................................... 395
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
6.1.6
6.1.7
6.1.8
6.1.9
6.1.10 Public Data Register Control................................................................... 402
6.1.11 Bypass Register ................................................................................... 402
6.1.12 Device ID Register................................................................................ 402
6.1.13 Boundary Scan Register ........................................................................ 403
Extended Debug Port (XDP) .............................................................................. 404
Absolute Maximum Ratings............................................................................... 405
7.1.1
7.1.2
DC Characteristics ........................................................................................... 406
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
Intel 5000X Chipset MCH Ballout ....................................................................... 413
Package Information........................................................................................ 455
Intel® 5000X Chipset System Block Diagram ........................................................ 21
Power-Up ......................................................................................................... 36
PWRGOOD ....................................................................................................... 36
Hard Reset ....................................................................................................... 37
RESETI# Retriggering Limitations ........................................................................ 37
Intel 5000X Chipset Clock and Reset Requirements.............................................. 35
JTAG Access to Configuration Space........................................................ 395
TAP Signals ......................................................................................... 395
Accessing the TAP Logic ........................................................................ 396
Reset Behavior of the TAP ..................................................................... 398
Clocking the TAP .................................................................................. 398
Accessing the Instruction Register .......................................................... 398
Accessing the Data Registers ................................................................. 400
Public TAP Instructions.......................................................................... 400
Public Data Instructions ........................................................................ 401
Thermal Characteristics......................................................................... 405
Power Characteristics............................................................................ 405
Clock DC Characteristics........................................................................ 407
FSB Interface DC Characteristics ............................................................ 408
FB-DIMM DC Characteristics .................................................................. 409
PCI Express/ ESI Interface DC Characteristics .......................................... 410
Miscellaneous DC Characteristics ............................................................ 411
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