QG5000X S L9TH Intel, QG5000X S L9TH Datasheet - Page 49
QG5000X S L9TH
Manufacturer Part Number
QG5000X S L9TH
Description
Manufacturer
Intel
Datasheet
1.QG5000X_S_L9TH.pdf
(458 pages)
Specifications of QG5000X S L9TH
Lead Free Status / RoHS Status
Compliant
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Table 3-1.
1. These accesses are used to select channel/DIMM based on the AMBASE register.
3.4.1
Table 3-2.
Notes:
Register Description
Intel
PCI Express Config
Txns (including
ESI)
PCI Express
MMCFG
on FSB
PCI Express
MMCFG
from ESI or PCI
Express
CPU/Inbound
CB_BAR MMIO
Access
CFGADR Register
CFC on
FSB
JTAG Config Access Source
SMBus Config
Access
Fixed MCH Memory
Mapped on FSB
MCH Register
Decoding
FB-DIMM Config
Cmds
®
5000X Chipset Memory Controller Hub (MCH) Datasheet
Configuration Address Bit Mapping
Device Identification for Intel 5000P Chipset, Intel 5000Z
Chipset, and Intel 5000V Chipset Components
All devices in the Intel® 5000X chipset MCH reside on Bus 0. The following table
describes the root device ID for different MCH versions.
Memory Control Hub ESI Device Identification
Intel 5000P Chipset
Intel 5000Z Chipset
Intel 5000V Chipset
Destination
Source
Not permitted to access MCH or FB-DIMM regs and will be master aborted.
Source
Source
Source
Source
Source
Destination
Destination
Destination
Source/
Component
Bus[7:0]
A[27:20]
0
Bus Number
[7:0]
CFGADR Register, see row above
Bus Number
[7:0]
Bus Number
[7:0]
0
00000000
A[23:15]
always 0
Bus
Enterprise South Bridge Interface
Enterprise South Bridge Interface
Enterprise South Bridge Interface
See Table
Device[4:0]
A[19:15]
8
DeviceID
[4:0]
DeviceID
[4:0]
Dev[4:0]
16
14-4
See Note
Device
Register Group
1
Function[2:0
]
A[14:12]
1
Function
Number[2:0]
Function
Number[2:0]
Func[2:0]
0
Function[2:0
]
Function
Extended
Register
Addr[3:0]
A[11:8]
A[11:8]
not present
Extended
Register
Addr[3:0]
Reg
Number
[11:8]
cannot
access
Dword
Offset[9:6]
Cannot
access
[11:8]
25C8h
25D0h
25D4h
DID
Dword
Offset
Register
[5:0]
A[7:3]
BE[7:4]
A[7:3]
BE[7:4]
Register
Address
[5:0]
Register
Address[7:2
]
Reg[7:2]
A[15:10]
Dword
Offset[5:0]
A[7:3]
BE[7:4]
0
0
Device
[5:0]
0
0
Functio
1st DW
BE[3:0]
BE[7:0]
BE[7:0]
Not present
BE[7:4]
Register
Address
[1:0]
command,
Register
Number
All accesses
are 4 byte
Byte[3:0]
BE[7:0]
Byte in
n
Dword
Fmt,
Type
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
Type
49
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