QG5000X S L9TH Intel, QG5000X S L9TH Datasheet - Page 273

• Manufacturer Part Number: QG5000X S L9TH
• Manufacturer: Intel

Specifications of QG5000X S L9TH

• Lead Free Status / RoHS Status: Compliant

Register Description
3.11.7
3.11.8
Intel
®
5000X Chipset Memory Controller Hub (MCH) Datasheet
PEX[7:2,0]IBDLYSYM: PEX Intel IBIST Delay Symbol
This register stores the value of the delay symbol used in lane inversion cross-talk
testing. Only valid PCI Express control characters/symbols are allowed for Intel IBIST
testing.
PEX[7:2,0]IBLOOPCNT: PEX Intel IBIST Loop Counter
This register stores the current value of the loop counter.
Device:
Function: 0
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function: 0
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
15:12
15:9
11:0
8:0
Bit
Bit
Attr
Attr
RW
RO
RV
RV
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
7-4
3-2, 0
38Ch
38Ch
Intel 5000P Chipset
4-5
0
38Ch
Intel 5000Z Chipset
3-2, 0
0
38Eh
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
38Eh
Intel 5000Z Chipset
7-4
0
38Eh
Intel 5000P Chipset
Default
Default
1BCh
000h
0h
0h
Reserved
DLYSYM: Delay Symbol
This is the 9-bit delay symbol value used (default is K28.5).
Reserved
LOOPCNTVAL: Loop Count Value
Once the Intel IBIST is engaged, loop counts are incremented when a set of 8
symbols has been received. If an error occurs, this register reflects the loop count
value of the errant Rx lane. If there is no error then this register reads 00h.
Note: Since each receiver is not deskewed with respect to the Intel IBIST pattern
generator we cannot have a coherent loop count value with N number of receivers
and only one loop counter. It would require additional logic to select which
receiver indicates the count.
Description
Description
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