QG5000X S L9TH Intel, QG5000X S L9TH Datasheet - Page 150

• Manufacturer Part Number: QG5000X S L9TH
• Manufacturer: Intel

Specifications of QG5000X S L9TH

• Lead Free Status / RoHS Status: Compliant

Table 3-36. Negotiated Link Width For Different PCI Express Ports After Training
3.8.11.9
150
1. The NLNKWD field is set to a default value corresponding to x4 internally within the Intel 5000P Chipset MCH.
1. Ports 3, 5, and 7 report 000000 as appropriate.
2. Ports 5, 6, and 7 report 000000 as appropriate.
PEXSLOTCAP[7:2, 0] - PCI Express Slot Capabilities Register
The Slot Capabilities register identifies the PCI Express specific slot capabilities.
Notes:
Notes:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
9:4
3:0
Note that this field is a don’t care until training is completed for the link. Software should not use this field to
determine whether a link is up (enabled) or not.
Bit
11
10
Device/Port
0,2,3,4,5,6,7
2,3,4,5,6,7
2,4,6
4
Attr
RO
RO
RO
RO
0, 2-3
0
7Eh
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
7Eh
Intel 5000Z Chipset
4-7
0
7Eh
Intel 5000P Chipset
Default
000100
1h
0
0
Negotiated Link Width
LNKTRG: Link Training
This field indicates the status of an ongoing link training session in the current
PCI Express port and is controlled by the Hardware.
0: indicates that the LTSSM is neither in “Configuration” nor “Recovery” states.
1: indicates Link training in progress (Physical Layer LTSSM is in
Configuration or Recovery state or the RLNK (retrain link) was set in
Section 3.8.11.7
Also refer to the BCTRL.SBUSRESET for details on how the Link training bit can
be used for sensing Hot-reset states.
TERR: Training Error
This field indicates the occurrence of a Link training error.
0: indicates no Link training error occurred.
1: indicates Link training error occurred.
NLNKWD: Negotiated Link Width
This field indicates the negotiated width of the given PCI Express link after
training is completed.
Only x1, x4, x8, and x16 link width negotiations are possible in the Intel
5000P Chipset MCH. Refer to
assignment after training is completed.
LNKSPD: Link Speed
This field indicates the negotiated Link speed of the given PCI Express Link:
0001- 2.5 Gb/s PCI Express link
Others -
x16
x1
x4
x8
Reserved
Intel
but training has not yet begun.
®
5000X Chipset Memory Controller Hub (MCH) Datasheet
Table 3-36
001000
010000
000001
000100
Description
Value
1
1
2
for the port and link width
Register Description