QG5000X S L9TH Intel, QG5000X S L9TH Datasheet - Page 248

• Manufacturer Part Number: QG5000X S L9TH
• Manufacturer: Intel

Specifications of QG5000X S L9TH

• Lead Free Status / RoHS Status: Compliant

3.9.25.17
248
FBD[3:2]IBRXPGCTL: FB-DIMM Intel IBIST Rx Pattern Generator
Control Register
This register contains bits to control the operation of the Rx pattern generator.
Device:
Function: 0
Offset:
Device:
Function: 0
Offset:
31:26
25:21
19:13
12:10
12:0
9:3
2:0
Bit
Bit
13
20
RWST
RWST
RWST
RWST
RWST
RWST
RWST
ROST
ROST
Attr
Attr
21
29Ch, 19Ch
22
2A0h, 1A0h
Default
04h
19h
19h
000
Default
0h
1h
0
0
0
OVRLOPCNT: Overall Loop Count[5:0]
0h: Send no Intel IBIST data in payload
1h-3Fh: The number of times to loop through all the patterns
CNSTGENCNT: Constant Generator Loop Counter[4:0]
00h: Disable constant generator output
01h: 1Fh The number of times the Modulo-N counter should be repeated before
going to the next pattern type. Each buffer transfer is composed of two frames
(loop counts of 24-bits each).
CNSTGENSET: Constant Generator Setting
0: Generate 0
1: Generate 1
MODLOPCNT: Modulo-N Loop Counter [7:0]
Each count represents 24-bits of the pattern specified by the MODPERIOD bit field.
00h: Disable Pattern Output
01h: 7Fh The number of times the Pattern Buffer should loop before going to the
next
MODPERIOD: Period of the Modulo-N counter
001: L/2 0101_0101_0101_0101_0101_0101
010: L/4 0011_0011_0011_0011_0011_0011
011: L/6 0001_1100_0111_0001_1100_0111
100: L/8 0000_1111_0000_1111_0000_1111
110: L/12 0000_0000_0000_1111_1111_1111
PATTLOPCNT: Pattern Buffer Loop Counter[6:0]
00h: Disable Pattern Output
01h-3Fh: The number of times the Pattern Buffer should be repeated before going
to the next pattern type. Each buffer transfer is composed of two frames (loop
counts of 24-bits each).
PTGENORD: Pattern Generation Order
000: Pattern Store + Modulo N Cntr + Constant Generator
001: Pattern Store + Constant Generator + Modulo N Cntr
010: Modulo N Cntr + Pattern Store + Constant Generator
011: Modulo N Cntr + Constant Generator + Pattern Store
100: Constant Generator + Pattern Store + Modulo N Cntr
101: Constant Generator + Modulo N Cntr + Pattern Store
110: Reserved
111: Reserved
rxerrstat: Receive error lane status for DFT.
This register records the error from lane 13 of this port.
rxerrstat: Receive error lane status.
This register records the errors from all lanes of this port.
Intel
®
5000X Chipset Memory Controller Hub (MCH) Datasheet
Description
Description
Register Description