QG5000X S L9TH Intel, QG5000X S L9TH Datasheet - Page 11

• Manufacturer Part Number: QG5000X S L9TH
• Manufacturer: Intel

Specifications of QG5000X S L9TH

• Lead Free Status / RoHS Status: Compliant

Intel® 5000X Chipset Memory Controller Hub (MCH) Datasheet
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5-10 Global Activation Throttling BW allocation as a function of GBLACTLM for a
5-11 Electrical Throttle Window as a Function of DIMM Technology ................................ 333
5-12 XAPIC Data Encoding ....................................................................................... 335
5-13 Intel 5000X Chipset XAPIC Interrupt Message Routing and Delivery ...................... 336
5-14 Chipset Generated Interrupts............................................................................ 344
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5-15 Options and Limitations.................................................................................... 354
5-16 PCI Express Credit Mapping for Inbound Transactions .......................................... 359
5-17 PCI Express Credit Mapping for Outbound Transactions ........................................ 360
5-18 MCH Reset Classes .......................................................................................... 363
5-19 Reset Sequences and Durations ........................................................................ 366
5-20 SMBus Transaction Field Summary .................................................................... 368
5-21 SMBus Address for Product Name Platform ......................................................... 374
5-22 SMBus Command Encoding............................................................................... 374
5-23 Status Field Encoding for SMBus Reads .............................................................. 375
5-24 MCH Supported SPD Protocols........................................................................... 379
5-25 I/O Port Registers in I/O Extender supported by Intel 5000X Chipset MCH ............. 383
5-26 Hot-Plug Signals on a Virtual Pin Port ................................................................. 384
5-27 Intel 5000X Chipset MCH Frequencies for Processors and Core ............................. 385
5-28 Intel 5000X Chipset MCH Frequencies for Memory .............................................. 385
5-29 Intel 5000X Chipset MCH Frequencies for PCI Express ......................................... 386
5-30 Clock Pins ...................................................................................................... 386
5-31 Intel 5000X chipset
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7-10 SMBus DC Characteristics................................................................................. 411
7-11 JTAG DC Characteristics ................................................................................... 411
7-12 1.5 V CMOS DC Characteristics ......................................................................... 411
7-13 3.3 V CMOS DC Characteristics ......................................................................... 411
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Memory Poisoning Table................................................................................... 314
x8 Double Device Detection Characteristics......................................................... 316
SPD Addressing............................................................................................... 317
AMB Thermal Status Bit Definitions .................................................................... 323
FB_DIMM Bandwidth as a Function of Closed Loop Thermal Throttling .................... 329
16384**1344 window with MC.GTW_Mode=0 (normal) ........................................ 332
PCI Express Link Width Strapping Options for Port CPCI Configuration in MCH ......... 354
TAP Signal Definitions ...................................................................................... 395
TAP Reset Actions ........................................................................................... 398
Public TAP Instructions..................................................................................... 401
Actions of Public TAP Instructions During Various TAP States................................. 402
Intel® 5000P chipset Device ID Codes ............................................................... 403
Absolute Maximum Ratings............................................................................... 405
Operating Condition Power Supply Rails ............................................................. 405
Analog and Bandgap Voltage and Current Specifications ....................................... 406
Clock DC Characteristics................................................................................... 407
FSB Interface DC Characteristics ....................................................................... 408
FB-DIMM Transmitter (Tx) Output DC Characteristics ........................................... 409
FB-DIMM Receiver (Rx) Output DC Characteristics ............................................... 409
PCI Express/ ESI Differential Transmitter (Tx) Output DC Characteristics ................ 410
PCI Express/ ESI Differential Receiver (Rx) Input DC Characteristics ...................... 410
Intel 5000X Chipset MCH Signals (by Ball Number) .............................................. 417
Intel 5000X Chipset MCH Signals (by Signal Name) ............................................. 436
Error List.......................................................................... 388
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