QG5000X S L9TH Intel, QG5000X S L9TH Datasheet - Page 303

• Manufacturer Part Number: QG5000X S L9TH
• Manufacturer: Intel

Specifications of QG5000X S L9TH

• Lead Free Status / RoHS Status: Compliant

Functional Description
Intel
®
5000X Chipset Memory Controller Hub (MCH) Datasheet
• Snoop Filter tracks total of 16 MB of cachelines (2
• 8K sets organized as one interleave via a 2 x 16 Affinity Set-Associativity array.
• 2 x 16 Affinity Set-Associativity will allocate/evict entries within the 16-way
• The array size of the snoop filter RAM is equivalent to 1MB plus 0.03MB of Pseudo-
• The Snoop Filter is operated at 2x of Intel 5000X chipset MCH core frequency, i.e.
• Pseudo-Least-Recently-Used (pLRU) replacement algorithm, with updates on
• Tag entries supporting a 40-bit internal physical address space. The MCH external
• Stores coherency state (EM) and Bus[1:0] for each valid cache line in the system.
• ECC coverage, with correction of single bit errors, detection of double bit errors
There are a total of 8K x 2 x 16 = 256K Lines (2
corresponding to the assigned affinity group if the SF look up is a miss. Each SF
look up will be based on 32-way (2x16 ways) look up.
Least-Recently-Used (pLRU) RAM.
Tag array size = 8192 sets * 4 bytes/set/group * (2 groups* 16 ways) = 1048576B
=1MB
~0.03MB
533MHz to provide 267 MLUU/s (where a Look-Up-Update operation is a read
followed by a write operation to the tag and pLRU arrays).
lookups, and invalidates.
address space is 36 bits.
The tracking algorithm utilizes conservative tracking (super-set tracking). The
processor can silently down grade a line state from E to S/I or S to I without any
action appearing on the FSB. Therefore, a line appearing in the SF as E states may
actually missed in the corresponding processor caches. Conversely a SF S-line will
never be found in E/M state in a processors L2 cache, or a SF miss will never be
found in M/E/S state in a processors L2 cache. The following is the summery of the
snoop-filter state definitions:
(SEC-DED).
pLRU array size = 8192 sets * 15 bits/set/group * (2 groups) = 30720B =
— The maximum lookup and update bandwidth of the Snoop Filter is equal to the
— The SF lookup latency is four SF-clocks or two Intel 5000X chipset MCH core
— Coherency state: the cache line is in E/M state if the bit is set; else, the line is
— If Bus[1:0]=00, the entry is invalid.
— If Bus[1:0]=01, the FSB0 processor(s) has ownership of the line.
— If Bus[1:0]=10, the FSB1 processor(s) has ownership of the line.
— If Bus[1:0]=11, both buses have ownership and the line must be shared by
— EM||Bus[1:0] =111 is a reserved definition.
— pLRU array does not need ECC protection. Bit failure will result in selecting
max request bandwidth from both FSB’s. The lookup and update bandwidth
from I/O coherent transactions have to share the bandwidth with both FSBs per
request weighted-round-robin arbitration.
clocks to support single snoop stall in idle condition (single request issued from
either bus). If both bus are making requests simultaneously, the snoop-filter
will always select bus 0 first. In such scenario, bus 0 request will have one
snoop-stall and bus 1 request will have two snoop-stalls.
in share state
both FSB processors (EM must be 0).
different entry than the pLRU selection and may affect the performance. There
are no correctness issue.
18
18
).
L2 lines).
303