QG5000X S L9TH Intel, QG5000X S L9TH Datasheet - Page 166

• Manufacturer Part Number: QG5000X S L9TH
• Manufacturer: Intel

Specifications of QG5000X S L9TH

• Lead Free Status / RoHS Status: Compliant

3.8.12.8
166
CORERRSTS[7:2, 0] - Correctable Error Status
This register identifies which unmasked correctable error has been detected. The error
is directed to the respective device correctable error bit in the PEX_NF_COR_FERR,
PEX_NF_COR_NERR registers (If the error is unmasked in the CORERRMSK register
defined in
Section
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
31:13
11:6
11:9
3:1
Bit
Bit
14
13
12
12
5
4
0
8
3.8.12.25.
RWCST
RWCST
RWST
RWST
RWST
RWST
RWST
RWST
Attr
Section
Attr
RV
RV
RV
RV
2-3
0
10Ch
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
10Ch
Intel 5000Z Chipset
4-7
0
10Ch
Intel 5000P Chipset
0, 2-3
0
110h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
110h
Intel 5000Z Chipset
4-7
0
110h
Intel 5000P Chipset
3.8.12.9). These registers are discussed starting from
Default
Default
0h
0h
000
0
0
0h
0
1
0
0
1
1
Reserved
IO16Err: Replay Timer Time-out Status
Reserved
IO15Err: Replay_Num Rollover Status
IO6Severity: Completion Time-out Severity
IO5Severity: Flow Control Protocol Error Severity
IO4Severity: Poisoned TLP Severity
Reserved
IO19Severity: Surprise Link Down Severity
IO0Severity: Data Link Protocol Error Severity
(See Figure 3-17 in PCI Express Base Specification, Revision 1.0a)
Reserved
IO3Severity:Training Error Severity
This field should not be used for setting Training error severity due to a
recent PCI Express Base Specification, Revision 1.0a Errata Dec 2003 to
remove training error. Hardware behavior is undefined.
Intel
®
5000X Chipset Memory Controller Hub (MCH) Datasheet
Description
Description
Register Description