QG5000X S L9TH Intel, QG5000X S L9TH Datasheet - Page 8

• Manufacturer Part Number: QG5000X S L9TH
• Manufacturer: Intel

Specifications of QG5000X S L9TH

• Lead Free Status / RoHS Status: Compliant

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5-10 Code Layout for Dual-Channel Branches ............................................................. 321
5-11 Thermal Throttling with THRMHUNT=1................................................................ 326
5-12 Thermal Throttling with THRMHUNT=0................................................................ 326
5-13 Thermal Throttling Activation Algorithm .............................................................. 328
5-14 XAPIC Address Encoding ................................................................................... 335
5-15 PCI Express Hot-Plug Interrupt Flow................................................................... 343
5-16 MCH to Intel 631xESB/632xESB I/O Controller Hub Enterprise South Bridge Interface....
5-17 x4 PCI Express Bit Lane.................................................................................... 350
5-18 ESI and PCI Express Ports 2 and 3 ..................................................................... 351
5-19 MCH to Intel 631xESB/632xESB I/O Controller Hub Port Configurations .................. 352
5-20 Intel 5000X Chipset PCI Express* High Performance x16 Port ............................... 353
5-21 PCI Express Packet Visibility By Physical Layer..................................................... 355
5-22 PCI Express Elastic Buffer (x4 Example).............................................................. 356
5-23 PCI Express Deskew Buffer (4X Example) ........................................................... 357
5-24 PCI Express Packet Visibility By Link Layer .......................................................... 358
5-25 PCI Express Packet Visibility By Transaction Layer................................................ 361
5-26 Intel 5000P Chipset Power Sequencing ............................................................... 362
5-27 Power-On Reset Sequence ................................................................................ 366
5-28 MCH SM Bus Interfaces .................................................................................... 367
5-29 DWORD Configuration Read Protocol (SMBus Block Write / Block Read,
5-30 DWORD Configuration Write Protocol (SMBus Block Write, PEC Disabled) ................ 371
5-31 DWORD Memory Read Protocol (SMBus Block Write / Bock Read, PEC Disabled)....... 372
5-32 DWORD Memory Write Protocol ......................................................................... 372
5-33 DWORD Configuration Read Protocol (SMBus Word Write / Word Read,
5-34 DWORD Configuration Write Protocol (SMBus Word Write, PEC Disabled)................. 372
Simplest Power Good Distribution ........................................................................40
Basic System Reset Distribution...........................................................................40
Basic INIT# Distribution .....................................................................................40
Conceptual Intel® 5000X chipset MCH PCI Configuration Diagram...........................46
Type 1 Configuration Address to PCI Address Mapping ............................................48
Intel 5000P Chipset MCH implementation of SRID and CRID Registers ......................77
PCI Express Configuration Space........................................................................ 102
PCI Express Hot-Plug Interrupt Flow................................................................... 157
FB-DIMM Reset Timing ..................................................................................... 228
Intel 5000P Chipset DMA Error/Channel Completion Interrupt Handling Flow............ 261
System Memory Address Map............................................................................ 278
Detailed Memory System Address Map ............................................................... 279
Interrupt /SMM Region ..................................................................................... 286
System I/O Address Space................................................................................ 296
System I/O Address Space................................................................................ 298
Snoop Filter .................................................................................................... 302
Minimum Two DIMM Configuration ..................................................................... 308
Next Two DIMM Upgrade Positions ..................................................................... 308
Single DIMM Operation Mode............................................................................. 309
Minimum Mirrored Mode Memory Configuration.................................................... 309
Mirrored Mode Next Upgrade ............................................................................. 310
FB-DIMM Channel Schematic............................................................................. 311
Connection of DIMM Serial I/O Signals................................................................ 317
Code Layout for Single-Channel Branches ........................................................... 320
347
PEC Disabled) ................................................................................................. 371
PEC Disabled) ................................................................................................. 372
Intel® 5000X Chipset Memory Controller Hub (MCH) Datasheet