QG5000X S L9TH Intel, QG5000X S L9TH Datasheet - Page 252

• Manufacturer Part Number: QG5000X S L9TH
• Manufacturer: Intel

Specifications of QG5000X S L9TH

• Lead Free Status / RoHS Status: Compliant

3.9.26
3.9.26.1
3.9.26.2
252
Serial Presence Detect Registers
There are two sets of the following registers, one set for each FB-DIMM branch. They
each appear in function 0 of different devices as shown in
SPD[1:0][1:0] - Serial Presence Detect Status Register
This register provides the interface to the SPD bus (SCL and SDA signals) that is used
to access the Serial Presence Detect EEPROM that defines the technology,
configuration, and speed of the DIMM’s controlled by the MCH.
SPDCMD[1:0][1:0] - Serial Presence Detect Command Register
A write to this register initiates a DIMM EEPROM access through the SPD bus.
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
11:8
7:0
Bit
15
14
13
12
Attr
RO
RO
RO
RO
RO
RV
21
0
76h, 74h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
22
0
76h, 74h
Intel 5000P Chipset
Default
00h
0h
0
0
0
0
RDO: Read Data Valid.
This bit is set by the AMB when the Data field of this register receives read data
from the SPD EEPROM after successful completion of an SPDR command. It is
cleared by the Intel 5000P Chipset MCH when a subsequent SPDR command is
issued.
WOD: Write Operation Done.
This bit is set by the Intel 5000P Chipset MCH when a SPDW command has been
completed on the SPD bus. It is cleared by the Intel 5000P Chipset MCH when a
subsequent SPDW command is issued.
SBE: SPD Bus Error.
This bit is set by the Intel 5000P Chipset MCH if it initiates an SPD bus transaction
that does not complete successfully. It is cleared by the AMB when an SPDR or
SPDW command is issued.
BUSY: Busy state.
This bit is set by the Intel 5000P Chipset MCH while an SPD command is executing.
Reserved.
DATA: Data.
Holds data read from SPDR commands.
Intel
®
5000X Chipset Memory Controller Hub (MCH) Datasheet
Description
Table 3-3.
Register Description