QG5000X S L9TH Intel, QG5000X S L9TH Datasheet - Page 134

• Manufacturer Part Number: QG5000X S L9TH
• Manufacturer: Intel

Specifications of QG5000X S L9TH

• Lead Free Status / RoHS Status: Compliant

3.8.10
3.8.10.1
3.8.10.2
134
PCI Express Message Signaled Interrupts (MSI) Capability
Structure
Message Signaled Interrupts (MSI) is an optional feature that enables a device to
request service by writing a system-specified message to a system-specified address in
the form of an interrupt message. The transaction address (for example, FEEx_xxxxh)
specifies the message destination and the transaction data specifies the message. The
MSI mechanism is supported by the following registers: the MSICAPID, MSINXPTR,
MSICTRL, MSIAR and MSIDR register described below.
MSICAPID[7:2, 0] - MSI Capability ID
MSINXPTR[7:2, 0]- MSI Next Pointer
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
7:0
7:0
Bit
Bit
Attr
Attr
RO
RO
0, 2-3
0
58h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
58h
Intel 5000Z Chipset
4-7
0
58h
Intel 5000P Chipset
0, 2-3
0
59h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
59h
Intel 5000Z Chipset
4-7
0
59h
Intel 5000P Chipset
Default
Default
05h
6Ch
CAPID: Capability ID
Assigned by PCI-SIG for message signaling capability.
NXTPTR: Next Pointer
This field is set to 6Ch for the next capability list (PCI Express capability
structure - PEXCAP) in the chain.
Intel
®
5000X Chipset Memory Controller Hub (MCH) Datasheet
Description
Description
Register Description