QG5000X S L9TH Intel, QG5000X S L9TH Datasheet - Page 357

• Manufacturer Part Number: QG5000X S L9TH
• Manufacturer: Intel

Specifications of QG5000X S L9TH

• Lead Free Status / RoHS Status: Compliant

Functional Description
Figure 5-23. PCI Express Deskew Buffer (4X Example)
5.13.7.5
5.13.8
Intel
®
5000X Chipset Memory Controller Hub (MCH) Datasheet
At reset, the delay of each lane in the deskew buffer is adjusted so that the symbols on
each lane are aligned. The receiver must compensate for the allowable skew between
lanes within a multi-lane link before delivering the data and control to the data link
layer. The deskew buffer is eight symbols deep to compensate for up to 20 ns of skew
between lanes.
Polarity Inversion
The PCI Express Base Specification, Revision 1.0a defines a concept called polarity
inversion. Polarity inversion allows the board designer to connect the D+ and D- lines
incorrectly between devices. The Intel 5000X chipset MCH supports polarity inversion.
Link Layer
The Data Link Layer of the PCI Express protocol is primarily responsible for data
integrity. This is accomplished with the following elements:
Figure 5-24
two types of packets: data link layer packets (DLLP) and Transaction Layer Packets
(TLP). Data Link layer packets are sent between the Link layers of each PCI Express
device and do not proceed to the Transaction Layer.
For Transaction layer packets (TLP), the link layer is responsible for prepending
sequence numbers and appending 32-bit CRC. The grayed out segment is not decoded
by the Data Link layer.
• Sequence number assignment for each packet
• ACK/NAK protocol to ensure successful transmission of every packet
• CRC protection of packets
• Time-out mechanism to detect “lost” packets
• Credit exchange
illustrates the scope of the link layer on a PCI Express packet. There are
Elastic Buffer
357