QG5000X S L9TH Intel, QG5000X S L9TH Datasheet - Page 342

• Manufacturer Part Number: QG5000X S L9TH
• Manufacturer: Intel

Specifications of QG5000X S L9TH

• Lead Free Status / RoHS Status: Compliant

5.9
342
Chipset Generated Interrupts
The Intel 5000X chipset MCH can trigger interrupts for chipset errors and for PCI
Express. For these events, the chipset can be programmed to assert pins that the
system can route to an APIC controller. The interrupts generated by the chipset are still
being defined. The following is a preliminary list of interrupts that can be generated.
1. Chipset error - Intel 5000X chipset MCH asserts appropriate ERR pin, depending
2. PCI Express error - Intel 5000X chipset MCH asserts appropriate ERR pin,
3. PCI Express hot-plug - Intel 5000X chipset MCH send Assert_HPGPE
on severity. This can be routed by the system to generate an interrupt at an
interrupt controller. (Intel 5000X chipset MCH pins ERR[2:0], MCERR, Intel
631xESB/632xESB I/O Controller Hub Reset). The ERR[0] pin denotes a correctable
and recoverable error. The ERR[1] pin denotes an uncorrectable error from Intel
5000X chipset MCH. The ERR[2] pin denotes a fatal error output from Intel 5000X
chipset MCH.
depending on severity. This can be routed by the system to generate an interrupt.
a. The Intel 5000X chipset MCH can receive error indications from the PCI Express
(Deassert_HPGPE) or generates an MSI or a legacy interrupt on behalf of a PCI
Express Hot-Plug event.
a. Intel 5000X chipset MCH generated Hot-Plug event such as PresDet change,
b. PCI Express Hot-Plug event from downstream.
— GPE message: Upon receipt of a Assert_GPE message from PCI Express, Intel
— Sideband signals: Some systems may choose to connect the interrupt via
ports. These are in the form of inbound ERR_COR/UNC/FATAL messages. Intel
5000X chipset MCH will assert the appropriate ERR signal just like any internal
Intel 5000X chipset MCH error as described in the RAS chapter.
Attn button, MRL sensor changed, power fault, and so forth. Each of these
events have a corresponding bit in the PCI Express Hot-Plug registers (Attention
Button, Power Indicator, Power Controller, Presence Detect, MRL Sensor, Port
Capabilities/Slot registers). This will generate an interrupt via the
assert_HPGPE, intx, or an MSI. Refer to
flow priority.
5000X chipset MCH will send assert_GPE signal to the ESI port. To generate an
SCI (ACPI), this signal will be routed to the Intel® 631xESB/632xESB I/O
Controller Hub appropriate GPIO pin to match the GPE0_EN register settings.
When the Hot-Plug event has been serviced, Intel 5000X chipset MCH will
receive a Deassert_GPE message. At this point the Intel 5000X chipset MCH
can deassert_GPE message to ESI. There needs to be a tracking bit per PCI
Express port to keep track of Assert/Deassert_GPE pairs. These tracking bits
should be OR’d together to determine whether to send the assert_GPE/
Deassert_GPE message. When Intel 5000X chipset MCH receives a matching
deassert_GPE message for that port, it will clear the corresponding tracking bit.
When all the tracking bits are cleared, the Intel 5000X chipset MCH will send a
Deassert_GPE message to the ESI port.
sideband signals directly to the Intel 631xESB/632xESB I/O Controller Hub. No
action is required from the Intel 5000X chipset MCH.
Intel
®
5000X Chipset Memory Controller Hub (MCH) Datasheet
Figure 5-15
for the Hotplug interrupt
Functional Description