QG5000X S L9TH Intel, QG5000X S L9TH Datasheet - Page 103

• Manufacturer Part Number: QG5000X S L9TH
• Manufacturer: Intel

Specifications of QG5000X S L9TH

• Lead Free Status / RoHS Status: Compliant

Register Description
3.8.8.1
Intel
®
5000X Chipset Memory Controller Hub (MCH) Datasheet
PCICMD[7:2, 0]- Command Register
This register defines the PCI 2.3 compatible command register values applicable to PCI
Express space.
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version: Intel 5000Z Chipset
Device:
Function:
Offset:
Version:
15:11
Bit
10
9
8
7
6
5
4
3
Attr
RW
RW
RW
RV
RO
RO
RO
RO
RO
0, 2-3
0
04h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
04h
4-7
0
04h
Intel 5000P Chipset
Default
0h
0
0
0
0
0
0
0
0
Reserved. (by PCI SIG)
INTxDisable: Interrupt Disable
Controls the ability of the PCI Express port to generate INTx messages.
This bit does not affect the ability of the
received at the PCI Express port. However, this bit controls the generation
of legacy interrupts to the DMI for PCI Express errors detected internally in
this port (for example, Malformed TLP, CRC error, completion time out, and
so forth) or when receiving root port error messages or interrupts due to
HP/PM events generated in legacy mode within the Intel 5000P Chipset
MCH. Refer to the INTP register in
Interrupt Pin Register” on page 119
1: Legacy Interrupt mode is disabled
0: Legacy Interrupt mode is enabled
FB2B: Fast Back-to-Back Enable
Not applicable to PCI Express and is hardwired to 0
SERRE: SERR Message Enable
his field handles the reporting of fatal and non-fatal errors by enabling the
error pins ERR[2:0].
1: Th
0: The
The errors are also enabled by the PEXDE
Section
In addition, for Type 1 configuration space header devices, for example,
Virtual P2P bridge), this bit, when set, enables transmission of
ERR_NONFATAL and ERR_FATAL error messages
Express interface. This bit does not affect the transmission of forwarded
ERR_COR messages. Refer to the Intel 5000P Chipset MCH RAS Error
Model.
IDSELWCC: IDSEL Stepping/Wait Cycle Control
Not applicable to PCI Express. Hardwired to 0.
PERRE: Parity Error Response Enable
When set, this field enables parity checking.
VGAPSE: VGA palette snoop Enable
Not applicable to PCI Express. Hardwired to 0.
MWIEN: Memory Write and Invalidate Enable
Not applicable to PCI Express. Hardwired to 0.
SCE: Special Cycle Enable
Not applicable to PCI Express. Hardwired to 0.
e
GNB
GNB
3.8.11.4.
is disabled from generating fatal/non-fatal errors.
is enabled to send fatal/non-fatal errors.
Description
Section 3.8.8.27, “INTP[7:2,0] -
for interrupt routing to DMI.
GNB
VCTRL register in
to route interrupt messages
1
forwarded from the PCI
103